v1.3.3 test faild: test_matrix_matmul_int16_non_transposed_b.py

[RyusukeYamano]

summary

I met test faild when running test whith is combined with nngen 1.3.3 and veriloggen 2.1.0. The test is test_matrix_matmul_int16_non_transposed_b.py

error message

$ python test_matrix_matmul_int16_non_transposed_b.py 
Traceback (most recent call last):
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 105, in visit
    r = ast.NodeVisitor.visit(self, node)
  File "/home/yamano/.pyenv/versions/3.8.2/lib/python3.8/ast.py", line 360, in visit
    return visitor(node)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 428, in visit_Call
    return self._call_Attribute(node)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 715, in _call_Attribute
    return method(*args, **kwargs)
  File "/usr03/work3/nngen_rc/nngen/nngen/operator/basic.py", line 1128, in control_sequence
    bt.read_modify_write(self.m, fsm, self.maxi,
  File "/usr03/work3/nngen_rc/nngen/nngen/basic_types.py", line 3042, in read_modify_write
    src_ram.orig_datawidth == maxi.datawidth) or
AttributeError: 'MultibankRAM' object has no attribute 'orig_datawidth'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "test_matrix_matmul_int16_non_transposed_b.py", line 73, in <module>
    rslt = matrix_matmul.run(a_shape, b_shape,
  File "/usr03/work3/nngen_rc/nngen/tests/matrix_matmul/matrix_matmul.py", line 67, in run
    targ = ng.to_veriloggen([c], 'matrix_matmul', silent=silent,
  File "/usr03/work3/nngen_rc/nngen/nngen/verilog.py", line 118, in to_veriloggen
    m = _to_veriloggen_module(objs, name, config, silent=silent)
  File "/usr03/work3/nngen_rc/nngen/nngen/verilog.py", line 194, in _to_veriloggen_module
    global_map_info, global_mem_map) = allocate(config, m, clk, rst,
  File "/usr03/work3/nngen_rc/nngen/nngen/verilog.py", line 452, in allocate
    control_cache, main_fsm = make_controls(
  File "/usr03/work3/nngen_rc/nngen/nngen/verilog.py", line 1578, in make_controls
    obj.run_control(main_fsm)
  File "/usr03/work3/nngen_rc/nngen/nngen/basic_types.py", line 1062, in run_control
    self.control.run(fsm)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/thread.py", line 122, in run
    self._synthesize_run_fsm(fsm, args, kwargs)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/thread.py", line 468, in _synthesize_run_fsm
    self.return_value = cvisitor.visit(_call_ast.body[0].value)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 105, in visit
    r = ast.NodeVisitor.visit(self, node)
  File "/home/yamano/.pyenv/versions/3.8.2/lib/python3.8/ast.py", line 360, in visit
    return visitor(node)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 425, in visit_Call
    return self._call_Name(node)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 448, in _call_Name
    return self._call_Name_function(node, name)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 646, in _call_Name_function
    ret = self._visit_next_function(tree)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 666, in _visit_next_function
    self.generic_visit(node)
  File "/home/yamano/.pyenv/versions/3.8.2/lib/python3.8/ast.py", line 368, in generic_visit
    self.visit(item)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 105, in visit
    r = ast.NodeVisitor.visit(self, node)
  File "/home/yamano/.pyenv/versions/3.8.2/lib/python3.8/ast.py", line 360, in visit
    return visitor(node)
  File "/home/yamano/.pyenv/versions/3.8.2/lib/python3.8/ast.py", line 370, in generic_visit
    self.visit(value)
  File "/usr03/work3/nngen_rc/.venv/lib/python3.8/site-packages/veriloggen/thread/compiler.py", line 116, in visit
    raise CompileError(e, code, node.lineno, node.col_offset,
veriloggen.thread.compiler.CompileError: "'MultibankRAM' object has no attribute 'orig_datawidth'" in "Call(func=Attribute(value=Name(id='self', ctx=Load()), attr='control_sequence', ctx=Load()), args=[], keywords=[])", line 2

environment

$ cat /etc/os-release 
NAME="Ubuntu"
VERSION="16.04.6 LTS (Xenial Xerus)"
ID=ubuntu
ID_LIKE=debian
PRETTY_NAME="Ubuntu 16.04.6 LTS"

python libs:

• Installing markupsafe (2.1.1)
• Installing jinja2 (3.1.2)
• Installing ply (3.11)
• Installing numpy (1.22.4)
• Installing protobuf (3.20.1)
• Installing pyparsing (3.0.9)
• Installing pyverilog (1.3.0)
• Installing typing-extensions (4.2.0)
• Installing attrs (21.4.0)
• Installing more-itertools (8.13.0)
• Installing onnx (1.12.0)
• Installing packaging (21.3)
• Installing pluggy (0.13.1)
• Installing py (1.11.0)
• Installing veriloggen (2.1.0)
• Installing wcwidth (0.2.5)
• Installing nngen (1.3.3)
• Installing pytest (5.4.3)

[shtaxxx]

Fixed in dfd0fcb82b6c641acdfe64e194d055cbe5a262c0