NNgen / nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Apache License 2.0
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v1.3.3 test faild: test_matrix_max_pool_int16_ksize7_stride7_global_par2.py #53

Closed RyusukeYamano closed 2 years ago

RyusukeYamano commented 2 years ago

summary

I met test faild when running test whith is combined with nngen 1.3.3 and veriloggen 2.1.0. The test is test_matrix_max_pool_int16_ksize7_stride7_global_par2.py

error message

$ python test_matrix_max_pool_int16_ksize7_stride7_global_par2.py 
NNgen: Neural Network Accelerator Generator (version 1.3.3)
[Configuration]
(AXI Master Interface)
  Data width   : 32
  Address width: 32
(AXI Slave Interface)
  Data width   : 32
  Address width: 32
[Schedule Table]
(Stage 0)
(Stage 1)
  <max_pool output_max_pool_0 dtype:int16 shape:(1, 1, 1, 15) ksize:(1, 7, 7, 1) strides:(1, 7, 7, 1) padding:'SAME'-(0, 0, 0, 0) par:2 default_addr:0 g_index:1 word_alignment:2 aligned_shape:(1, 1, 1, 16) scale_factor:1.000000>
  | <placeholder act dtype:int16 shape:(1, 7, 7, 15) default_addr:64 g_index:2 word_alignment:2 aligned_shape:(1, 7, 7, 16) scale_factor:1.000000>
[RAM (spec: num)]
  32-bit 128-entry 2-port 1-bank RAM: 50
[Substream (spec: num)]
  ('_max', (16, 0, True, 49)): 2
[Stream (spec: num)]
  (((<class 'nngen.operator.pool.max_pool'>, <dtype int16>), <dtype int16>, 2), 7, 7, 2): 1
[State IDs in main_fsm]
  (3, 4, 'act', 'None')
  (8, 10, 'output_max_pool_0', 'control_max_pool_1')
[Control (name (# states: num))]
  main_fsm (# states: 16)
  control_max_pool_1 (# states: 35)
[Register Map]
    0 (R ): header0 (default: 0x00000000)
    4 (R ): header1 (default: 0x00000000)
    8 (R ): header2 (default: 0x00000000)
   12 (R ): header3 (default: 0x00000000)
   16 ( W): Start (set '1' to run)
   20 (R ): Busy (returns '1' when running)
   24 ( W): Reset (set '1' to initialize internal logic)
   28 (R ): Opcode from extern objects to SW (returns '0' when idle)
   32 ( W): Resume extern objects (set '1' to resume)
   36 (R ): Interrupt Status Register
   40 ( W): Interrupt Enable Register
   44 ( W): Interrupt Acknowledge Register
   48 (R ): State Counter
   52 ( W): Count Target
   56 ( W): Count Divider
   60 (  ): Reserved ...
  120 (  ): ... Reserved
  124 (R ): Address space amount
  128 (RW): Global address offset (default: 0)
  132 (RW): Address of temporal storages (size: 0B)
  136 (RW): Address of output (max_pool) 'output_max_pool_0' (size: 64B, dtype: int16, shape: (1, 1, 1, 15), alignment: 2 words (4 bytes)), aligned shape: (1, 1, 1, 16)
  140 (RW): Address of placeholder 'act' (size: 2KB, dtype: int16, shape: (1, 7, 7, 15), alignment: 2 words (4 bytes)), aligned shape: (1, 7, 7, 16)
[Default Memory Map (start - end)] (entire range: [0 - 1663], size: 2KB)
  [   0 -   63]: output (max_pool) 'output_max_pool_0' (size: 64B, dtype: int16, shape: (1, 1, 1, 15), alignment: 2 words (4 bytes)), aligned shape: (1, 1, 1, 16)
  [  64 - 1663]: placeholder 'act' (size: 2KB, dtype: int16, shape: (1, 7, 7, 15), alignment: 2 words (4 bytes)), aligned shape: (1, 7, 7, 16)
# start
# end
# execution cycles:         712
NG (           0           0           0           0 ) orig:            x  check:            5
NG (           0           0           0           1 ) orig:            x  check:            6
NG (           0           0           0           2 ) orig:            x  check:            7
NG (           0           0           0           3 ) orig:            x  check:            8

environment

$ cat /etc/os-release 
NAME="Ubuntu"
VERSION="16.04.6 LTS (Xenial Xerus)"
ID=ubuntu
ID_LIKE=debian
PRETTY_NAME="Ubuntu 16.04.6 LTS"

python libs:

shtaxxx commented 2 years ago

Fixed in 2dff33e96d1bcb922edc8b83404ce2206f418772