An access width of 256b for the DMA was implemented, because it should improve the data bus performance. Need to be tested if it works properly to later check if the speed was improved.
This modification is implemented, in commit eef53d215239a7a34033a7cb38fe7e9099853c4d, and synthesized as HW V21, in commit c17fe630f9f1e0e014f4a27919609a23bf87a99c.
Change Log:
Changed the DMA bus width to 256b and it access type to aligned.
Remaining:
@ericolucasm to test the HW V21 to check the modification works.
Test Procedure:
[ ] Do a full normal test with the SimuCam and verify if all 638 packets are being transmitted per CCD [if not, a bug was introduced in the system. If all 638 packets are transmitted, the issue can be closed].
An access width of 256b for the DMA was implemented, because it should improve the data bus performance. Need to be tested if it works properly to later check if the speed was improved. This modification is implemented, in commit eef53d215239a7a34033a7cb38fe7e9099853c4d, and synthesized as HW V21, in commit c17fe630f9f1e0e014f4a27919609a23bf87a99c.
Change Log:
Remaining:
Test Procedure:
Hardware Programming File: