A simplified burst write was implemented in the fee buffers, because it should improve the data bus performance. Need to be tested if it works properly to later check if the speed was improved.
This modification was implemented, simulated, both in commit bb1422f24ce0dee1bbb86f301860ade422057e0e, and synthesized as HW V22, in commit 23a8c0b56bc93ee4e7d425c10d0beb5fbc641126.
Change Log:
Added a burstcount signal to the fee avalon write and .tcl.
Modified the fee avalon write to support a simplified burst.
Remaining:
@ericolucasm to test the HW V22 to check the modification works.
Test Procedure:
[ ] Do a full normal test with the SimuCam and verify if all 638 packets are being transmitted per CCD [if not, a bug was introduced in the system. If all 638 packets are transmitted, the issue can be closed].
A simplified burst write was implemented in the fee buffers, because it should improve the data bus performance. Need to be tested if it works properly to later check if the speed was improved. This modification was implemented, simulated, both in commit bb1422f24ce0dee1bbb86f301860ade422057e0e, and synthesized as HW V22, in commit 23a8c0b56bc93ee4e7d425c10d0beb5fbc641126.
Change Log:
Remaining:
Test Procedure:
Hardware Programming File: -SimuCam_V22_20190224_HW.sof: https://github.com/NSEE/SimuCam_Development/blob/23a8c0b56bc93ee4e7d425c10d0beb5fbc641126/G3U_HW_V02_2GB/Quartus_Project/output_files/SimuCam_V22_20190224_HW.sof