Sometimes, if used intensively, PLL goes out of locking and never returns to it.
Appnote "Si5351 – Modifying the Feedback Multisynth Dividers Silicon Labs Timing Knowledge Base Article # 311668" states that:
"any changes to the feedback Multisynth will require a PLL reset. PLLA and PLLB are reset by setting register 177 bits 5 and 7 respectively to 1."
Please add these resets to the code where the PLL multisynths are updated.
Sometimes, if used intensively, PLL goes out of locking and never returns to it.
Appnote "Si5351 – Modifying the Feedback Multisynth Dividers Silicon Labs Timing Knowledge Base Article # 311668" states that: "any changes to the feedback Multisynth will require a PLL reset. PLLA and PLLB are reset by setting register 177 bits 5 and 7 respectively to 1."
Please add these resets to the code where the PLL multisynths are updated.