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NVIDIA / jetson-rdma-picoevb

Minimal HW-based demo of GPUDirect RDMA on NVIDIA Jetson AGX Xavier running L4T
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Vivado block sources missing #5

Closed rtheyyunmw closed 4 years ago

rtheyyunmw commented 4 years ago

For both the fpga folders I am unable to recreate the block diagram. Not sure if it is because the following files except top.v are missing?

  1. The following remote source files that were added to the original project:- #

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/top.v"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/axi_gpio_0/axi_gpio_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/ddr4_0/ddr4_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/xdma_0/xdma_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/axi_crossbar_0/axi_crossbar_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/proc_sys_reset_0/proc_sys_reset_0.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/vivado-project.srcs/sources_1/ip/axi_gpio_1/axi_gpio_1.xci"

    "/home/scratch.swarren_t18x/jetson-rdma-picoevb/fpga-htg-k800/htg-k800.xdc"

swarren commented 4 years ago

The project deliberately isn't a block diagram project. It uses top.v to represent the top-level connections. Did you run git-to-project.sh to generate the Vivado project files from the checked-in Tcl scripts? See README.md in the top-level directory for instructions.

rtheyyunmw commented 4 years ago

Stephen, Thank you very much for your response. I was trying to check it out from my Windows machine. I think I understand it now. Out of curiosity, why was the decision made to not use block diagram. I am not an expert in writing HDL Code by hand, but I have use block diagram in some of the work that I have done before. One more question – I assume that both the boards use the same PCIe Vendor/Device ID and can be used by the same driver?

From: Stephen Warren notifications@github.com Sent: Monday, July 13, 2020 11:17 AM To: NVIDIA/jetson-rdma-picoevb jetson-rdma-picoevb@noreply.github.com Cc: Roger Theyyunni rtheyyun@mathworks.com; Author author@noreply.github.com Subject: Re: [NVIDIA/jetson-rdma-picoevb] Vivado block sources missing (#5)

The project deliberately isn't a block diagram project. It uses top.v to represent the top-level connections. Did you run git-to-project.sh to generate the Vivado project files from the checked-in Tcl scripts? See README.md in the top-level directory for instructions.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/NVIDIA/jetson-rdma-picoevb/issues/5#issuecomment-657621025, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ANU4YZAUTWO7BKTHRDF2R33R3MQNDANCNFSM4OX7DHEQ.

swarren commented 4 years ago

I personally find Verilog top blocks much easier to deal with than the block GUI w.r.t integrating custom code, interfacing with source control, general interaction with the tools, etc. This project is a sample, not a production solution, so you're free to create a block design based on it if you want; this is an implementation detail that doesn't affect the interaction with PCIe, Jetson, or GPU.

Each FPGA project uses the same vendor/device ID, but a different subdevice ID. See the list at: https://github.com/NVIDIA/jetson-rdma-picoevb/blob/master/kernel-module/picoevb-rdma.c#L1255

I assume this issue can be closed now?

rtheyyunmw commented 4 years ago

Yes, of course please close it. Thank you for your help

From: Stephen Warren notifications@github.com Sent: Tuesday, July 14, 2020 2:51 PM To: NVIDIA/jetson-rdma-picoevb jetson-rdma-picoevb@noreply.github.com Cc: Roger Theyyunni rtheyyun@mathworks.com; Author author@noreply.github.com Subject: Re: [NVIDIA/jetson-rdma-picoevb] Vivado block sources missing (#5)

I personally find Verilog top blocks much easier to deal with than the block GUI w.r.t integrating custom code, interfacing with source control, general interaction with the tools, etc. This project is a sample, not a production solution, so you're free to create a block design based on it if you want; this is an implementation detail that doesn't affect the interaction with PCIe, Jetson, or GPU.

Each FPGA project uses the same vendor/device ID, but a different subdevice ID. See the list at: https://github.com/NVIDIA/jetson-rdma-picoevb/blob/master/kernel-module/picoevb-rdma.c#L1255https://github.com/NVIDIA/jetson-rdma-picoevb/blob/master/kernel-module/picoevb-rdma.c#L1255

I assume this issue can be closed now?

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