Questions about the latency numbers in src/graph/tuning.cc

The file src/graph/tuning.cc contains a model that computes how long GPU collectives using NCCL should take. To compute this, "ncclTopoTuneModel" requires information about hardware and base latencies, which are given in units of microseconds earlier in the same file:

// Tree { LL, LL128, Simple } , Ring { LL, LL128, Simple }
static const float baseLat  [NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS] = {
       {  6.8, 14.0,    0 }, {  6.6, 14.0,  8.4 },  // Tree, Ring
       {    0,    0,    0 }, {    0,    0,    0 },  // Collnet Direct, Chain
       {    0,    0,    0 }, {    0,    0,    0 }}; // NVLS, NVLS Tree

// NVLink, PCI, Network
#define NCCL_HW_NVLINK 0
#define NCCL_HW_PCI 1
#define NCCL_HW_NET 2
static float hwLat [3][NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS] =
{ /* NVLINK */
  { /* Tree (LL/LL128/Simple)*/ { .6, 1.25, 28 }, /* Ring (LL/LL128/Simple)*/ { .6, 1.9, 3.4 },
    /* CollNetDirect (Simple)*/ { 0, 0, 3.7 }, /* CollNetChain (Simple)*/ { 0, 0, 2.8 },
    /* NVLS */ { 0, 0, 25 }, /* NVLSTree */ { 0, 0, 25 } },
  /* PCI */
  { /* Tree (LL/LL128/Simple)*/ { 1.0, 1.9, 28 }, /* Ring (LL/LL128/Simple)*/ { 1.0, 2.5, 5.7 },
    /* CollNetDirect (Simple)*/ { 0, 0, 3.7 }, /* CollNetChain (Simple)*/ { 0, 0, 2.8 },
    /* NVLS */ { 0, 0, 0 }, /* NVLSTree */ { 0, 0, 0 } },
  /* NET */
  { /* Tree (LL/LL128/Simple)*/ { 5.0, 8.5, 28 }, /* Ring (LL/LL128/Simple)*/ { 2.7, 4.0, 14.0 },
    /* CollNetDirect (Simple)*/ { 0, 0, 31 }, /* CollNetChain (Simple)*/ { 0, 0, 30 },
    /* NVLS */ { 0, 0, 18 }, /* NVLSTree */ { 0, 0, 14 } }
};

I had a few questions about these numbers:

There's no architecture dependence for the hwLat figures, in contrast to the bandwidth numbers that follow them in the file. Is this because the latencies do not depend on the architecture of the GPU (i.e. Volta/Ampere/Hopper)?
If the latency numbers do not depend on architecture, then what are they based on instead? My guess is that at least the network latencies should have something to do with what the InfiniBand technology that is used is able to support, but I'm not totally sure that this is the bottlenecking factor. If possible, I'd like to have a better understanding of the lower-level steps involved in executing a GPU collective like all-reduce using NCCL, and which individual steps add up to produce the baseLat and hwLat numbers quoted above.
How have these latency numbers changed over time? For example, how much faster is it to reduce a trivial amount of information (e.g. 8 bytes) across a node of 8 H100s today compared to a node of 8 A100s in 2020 or 2021?

If there's a reference which explains this in detail, I would be happy if someone could direct me to it.

NVIDIA / nccl

Questions about the latency numbers in src/graph/tuning.cc #1334