Closed mahmoodn closed 2 years ago
Sorry for not answering this earlier.
The reason the nvbit_add_call is added multiple times is that in this example we are potentially instrumenting the same instruction multiple times, one for each memory reference.
The only instruction that currently support more than one memory reference is LDGSTS like you mentioned, which will be instrumented twice. All the other memory instructions are only instrumented once.
Closing this issue, since it is not an nvbit issue "per-se" but rather a request for explanation of how a specific tool works.
Hi I have difficulty in understanding the following piece of code
For LDGSTS, there are two MREF operands, so the loop iterates twice. Why opcode_id is pushed two times then? Also, what happen after each nvbit_add_call* function?
BTW, With respect to the async-copy logic, I expect that "LDGSTS [R1], [R2]" means sh_mem[R1] <- gl_mem[R2]. Is that correct? Are there more operands for async-copy?