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NVlabs / timeloop

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
https://timeloop.csail.mit.edu/
BSD 3-Clause "New" or "Revised" License
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New Feature Request: allow partial ordering specification in permutation #132

Closed hqjenny closed 1 year ago

hqjenny commented 2 years ago

For problem with 'ABCXYZN' dimension, we'd like to specify a partial order of XYZ. Currently the following specification implies that the XYZ will be the first three dimensions and the permitted permutation is XYZ_ _ _ _.

- target: MainMemory
    type: temporal
    permutation: XYZ

We would like to allow permutations like X_Y_ _Z_ or X_ _Y_ _Z. It is helpful for us to eliminate symmetrical mappings in exhaustive mapping search.

vmiheer commented 2 years ago

Hello @hqjenny, I was wondering if there are examples of different permutation constraints (especially those involving _) in any timeloop/accelergy exercises? If I am correct, the permutation constraints are not applied to the innermost (register level)?

hqjenny commented 2 years ago

@vmiheer Here explains how permutation works: https://timeloop.csail.mit.edu/timeloop/input-formats/mapping. There is no example with unspecified permutation mapper constraints yet, but it works as I mentioned. If only XYZ is specified in a problem with dimensions XYZPQN, then it fixes the permutation of inner loops to XYZ (inner to outer order) and will explore different PQN orders in the outer loops. If I understand correctly, permutation should work for all memory levels including Register so we can specify the order of data to run on the Register.

angshuman-parashar commented 2 years ago

Both prefix and suffix (separated by _) are now supported. See commit 96cc39ba7a0e8a667711cd623c4d8b4d934499b2, there is also an example in the commit notes.