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NVlabs / timeloop

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
https://timeloop.csail.mit.edu/
BSD 3-Clause "New" or "Revised" License
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[Question] Relationship between SRAM bandwidth and width/nports #139

Closed troore closed 2 years ago

troore commented 2 years ago

Hi @angshuman-parashar

Thanks for the great tool! I am using Timeloop for architecture PPA evaluation, and I may have a question similar to issues #60 and #108. These two issues give me some hints but I still want to confirm again, especially for SRAM.

I find that when calculating number of cycles, the slowdown will not change if we do not specify the bandwidth attribute. However, we know that SRAM bandwith could be simply derived from width and nports (width*nports/cycle). Then I have two questions:

  1. What if the specified read_bandwidth/write_bandwidth is not equal to width*nports/cycle?
  2. If the witdh and nports are not used for bandwidth calculation, are they mainly for area and power calculation?

Thanks, troore

angshuman-parashar commented 2 years ago

Correct, width and nports are currently not used for bandwidth calculation. The width (along with depth) is used to compute total mappable buffer capacity, and width and nports are passed through to Accelergy for area and energy estimation.

I think it makes sense to be able to derive bandwidth from those parameters. Or, if bandwidth is already specified, we could perform an assertion check that the width/ports specs can actually supply that bandwidth. If you feel like contributing towards this, please take a look at src/model/buffer.cpp, you should be able to easily find the location where these parameters are read in and processed.

troore commented 2 years ago

Thanks for the confirmation. The assertion check way is awesome. I will submit a changeset to derive bandwith from width/ports when bandwidth is not specified.

Thanks again, troore