Plan to support other arch configurations

[WVik]

Hello,

Thanks a lot for the amazing work, the tutorials and the examples with Timeloop. I'm relatively new to this area and slowly starting to write different architectures. I'm not sure how active this repository is now, but I wanted to ask if there is any place where I can find the SCNN architecture as described in this paper: https://arxiv.org/abs/1708.04485 I find some of the intricacies of the paper difficult to write and it would be immensely helpful to see an example of this.

Thank you again!

[nellie-wu]

The currently available open-source accelerator architecture specifications can be found at

• https://github.com/Accelergy-Project/timeloop-accelergy-exercises/tree/master/workspace/baseline_designs/example_designs
• https://github.com/Accelergy-Project/micro22-sparseloop-artifact/tree/main/workspace/2022.micro.artifact

We have not open-sourced the SCNN design yet due to the special handling needed for its input stationary dataflow, and we are working on getting more designs available.

Meanwhile, it might be helpful to take a look at the specifications of the DSTC design, as it shares a similar source of overhead as SCNN does -- both designs introduce a significant number of updates to accumulation buffer (https://github.com/Accelergy-Project/micro22-sparseloop-artifact/tree/main/workspace/2022.micro.artifact/evaluation_setups/fig13_dstc_setup).