NVlabs / timeloop

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
https://timeloop.csail.mit.edu/
BSD 3-Clause "New" or "Revised" License
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Support for Position skipping (DSTC) in timeloop-mapper #224

Open pruhnuhv opened 9 months ago

pruhnuhv commented 9 months ago

I've built Timeloop v3.0.1 from source, and I'm using the input_specs for DSTC as per your Micro-22 Artifact. On the first try, trying to map a SpMM kernel onto DSTC fails with this error:

Architecture configuration complete. terminate called after throwing an instance of 'YAML::InvalidNode' what(): invalid node; this may result from using a map iterator as a sequence iterator, or vice-versa

On further examination, I realize that it is the sparse optimization configuration that is causing this error. And rightly so, passing the other input files to timeloop-mapper apart from the sparse optimization file makes it work. But we need it to work with sparse optimization. Now, after a bit of debugging, I see that it is failing during the optimization steps at the last level of the memory hierarchy. On referring to the Micro paper, I see that the last level skipping of A <-> B is not properly referred to in this configuration and I correspondingly add that. Now the next issue is the fact that the action-optimization "position-skipping" is no longer a valid type in Timeloop.

ERROR: LineBuffer: storage action optimization type not recognized... timeloop-mapper: src/model/sparse-optimization-parser.cpp:553: void sparse::ParseActionOptimizationInfo(sparse::SparseOptimizationInfo&, const config::CompoundConfigNode&, const model::Engine::Specs&): Assertion `false' failed.

Changing the type from "position-skipping" to "skipping", I can get the mapper to start the mapping space search (currently trying for a workload with M, K, N = 1024, 256, 196) however it fails at one point.

... [ 2] Utilization = 0.03 | pJ/Algorithmic-Compute = 4.308 | pJ/Compute = 15.384 | L3[ABZ] M64 - L2[AB] N49 M16 - L1[Z] K4 N2 - L0[] K64 N2Y [ 6] Utilization = 0.06 | pJ/Algorithmic-Compute = 35.270 | pJ/Compute = 54.721 | L3[ABZ] K2 M8 - L2[A] K2 N2 M16 - L1[] K16 M8 - L0[] N98 K4Y timeloop-mapper: src/loop-analysis/tiling-tile-info.cpp:243: double tiling::DataMovementInfo::GetExpectedAggregatedMetaDataTileOccupancy() const: Assertion `expected_metadata_occupancy.size() > 0' failed. [1] 141926 abort (core dumped) timeloop-mapper architecture.yaml mapper.yaml prob.yaml sparse-opt.yaml -o

I am not even sure if "skipping" is a like-for-like replacement for "position-skipping" in the DSTC architecture. I've attached the sparse-opt.txt config file here. The rest of the config stays the same from the original DSTC setup in the MICRO artifact.

angshuman-parashar commented 8 months ago

position-skipping is a feature that we unfortunately have not had the opportunity to pull into the mainline dev branch yet. It's only available in the MICRO artifact version, which is based off of v2.0. Note that position skipping is supported only in the innermost tiling level, and was coded specifically to model the DSTC and SCNN dataflows. If you do not need any of the v3.x features (specifically Ruby) then we recommend using this artifact version.