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NVlabs / timeloop

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.
https://timeloop.csail.mit.edu/
BSD 3-Clause "New" or "Revised" License
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The register in timeloop is accessible to all PEs, right? #263

Open ziyuhuang123 opened 2 months ago

ziyuhuang123 commented 2 months ago

The register in timeloop is accessible to all PEs, right?

angshuman-parashar commented 2 months ago

Are you talking about a specific hardware configuration? Timeloop has no built-in notion of a "register" or a "PE" -- these are things that a user can name when designing an architecture for Timeloop to model.