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NXP / i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
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ORUN issue #11

Closed prats2018 closed 5 years ago

prats2018 commented 5 years ago

Hi, I am observing tb_orun during read . The description says The internal from-bus buffer/FIFO was overrun (too many chars coming in and not drained by the app fast enough). How to resolve this.

Thanks Prathusha

pkimelman-nxp commented 5 years ago

To bus overrun means you are writing to the TX FIFO too fast. The software should be using the TX status or interrupt. If polling, then read the STATUS register and check of TX has space. If using the interrupt you can fill it the same way. The datactrl register will also tell you how much space. Note that you can configure the TX FIFO size to be whatever you want.

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Hi, I am observing tb_orun during read . The description says The internal from-bus buffer/FIFO was overrun (too many chars coming in and not drained by the app fast enough). How to resolve this.

Thanks Prathusha

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prats2018 commented 5 years ago

Thanks, we have increased the Internal FIFO Threshold to 4.So overrun error is resolved. But, now there is another issue, while reading , we are getting underrun issue..:( Did we miss any settings? Can you check this waveform attached here? Note: We are not configuring any APB registers. sdr_Slv_ok bit is tied to 1. i2c_slave

pkimelman-nxp commented 5 years ago

The underrun simply means it ran out of data, but was not told last one was the last (end). You need to write END if it is the end of the data you want to send. You can either use WDATAB with the END bit, or use WDATABE for this. If using half-words, then WDATAH and WDATAHE.

On Jul 19, 2019, at 2:07 AM, prats2018 notifications@github.com<mailto:notifications@github.com> wrote:

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Thanks, we have increased the Internal FIFO Threshold to 4.So overrun error is resolved. But, now there is another issue, while reading , we are getting underrun issue..:( Did we miss any settings? Can you check this waveform attached here? Note: We are not configuring any APB registers. sdr_Slv_ok bit is tied to 1. [i2c_slave]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fuser-images.githubusercontent.com%2F41048446%2F61523839-c2839200-aa32-11e9-876c-61eb59d23590.png&data=02%7C01%7Cpaul.kimelman%40nxp.com%7C205d03f774a84d78978608d70c28977d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636991240794113962&sdata=%2BCuvSRws5obssaK3rdRyrLaaHIa0vW5fMZ1MPHOAU8k%3D&reserved=0

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