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NXP / i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
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I3C TIMING CONTROL #18

Closed Jiahua-Gong closed 5 years ago

Jiahua-Gong commented 5 years ago

This source do not have

pkimelman-nxp commented 5 years ago

Correct. The free version does not include either of the timing control blocks, nor hdr-ddr, nor dma.

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ggpf320 commented 5 years ago

Hi Paul Can it be understood that the IBI with Mandatory Data Byte is not supported in free version?

pkimelman-nxp commented 5 years ago

It is supported. The CTRL reg is active to support in the APB version, and the autonomous makes available as well. Only the time stamp adder is not supported.

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Jiahua-Gong commented 5 years ago

I have verified the coded.It’s very good!But I’m confused about IBI generation.Why the IBI generation is the clock slow domain?Thank you! 

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------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Thu,Oct 17,2019 0:22 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

It is supported. The CTRL reg is active to support in the APB version, and the autonomous makes available as well. Only the time stamp adder is not supported.

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On Oct 16, 2019, at 8:22 PM, ggpf320 <notifications@github.com> wrote:



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Hi Paul Can it be understood that the IBI with Mandatory Data Byte is not supported in free version?

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Jiahua-Gong commented 5 years ago

Another question about I3C master.I noticed Nxp have a MCU with i3c master.When the MCU go to mass production ？I want to buy this MCU for testing i3c communication.

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------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Thu,Oct 17,2019 0:22 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

It is supported. The CTRL reg is active to support in the APB version, and the autonomous makes available as well. Only the time stamp adder is not supported.

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On Oct 16, 2019, at 8:22 PM, ggpf320 <notifications@github.com> wrote:



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pkimelman-nxp commented 5 years ago

Are you using the autonomous or APB slave? The IBI starts from the system clock so you can initiate it - PCLK or SlowCLK. This is necessary anyway. But it is also because it allows us to pull SDA low even without an SCL - a feature of i3c. That is, when bus is stopped we pull SDA low to get the Master to emit the START clock.

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On Oct 17, 2019, at 4:26 AM, Jiahua notifications@github.com wrote:



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I have verified the coded.It’s very good!But I’m confused about IBI generation.Why the IBI generation is the clock slow domain?Thank you! 

发自我的iPhone

------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Thu,Oct 17,2019 0:22 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

It is supported. The CTRL reg is active to support in the APB version, and the autonomous makes available as well. Only the time stamp adder is not supported.

Sent from my iPhone

On Oct 16, 2019, at 8:22 PM, ggpf320 <notifications@github.com> wrote:



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Hi Paul Can it be understood that the IBI with Mandatory Data Byte is not supported in free version?

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Jiahua-Gong commented 5 years ago

I use the autonomous as my top module,If my system is only scl clock,we can also use comb logic to pull down.Even we can use asm to generation this start.

发自我的iPhone

------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Thu,Oct 17,2019 10:58 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

Are you using the autonomous or APB slave? The IBI starts from the system clock so you can initiate it - PCLK or SlowCLK. This is necessary anyway. But it is also because it allows us to pull SDA low even without an SCL - a feature of i3c. That is, when bus is stopped we pull SDA low to get the Master to emit the START clock.

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On Oct 17, 2019, at 4:26 AM, Jiahua <notifications@github.com> wrote:



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I have verified the coded.It’s very good!But I’m confused about IBI generation.Why the IBI generation is the clock slow domain?Thank you!&nbsp;

发自我的iPhone

------------------ Original ------------------ From: Paul Kimelman <notifications@github.com&gt; Date: Thu,Oct 17,2019 0:22 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com&gt; Cc: Jiahua <1016765625@qq.com&gt;, Author <author@noreply.github.com&gt; Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

It is supported. The CTRL reg is active to support in the APB version, and the autonomous makes available as well. Only the time stamp adder is not supported.

Sent from my iPhone

On Oct 16, 2019, at 8:22 PM, ggpf320 <notifications@github.com&gt; wrote:



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Hi Paul Can it be understood that the IBI with Mandatory Data Byte is not supported in free version?

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pkimelman-nxp commented 5 years ago

I am not sure what “asm” means here. But, you can generate a fake clock if you want. The CLK_SLOW is there just to synchronize the net. I agree that for a purely clock-less device which only relies on SCL, this is not generally needed, but that case is hard to see how it can work with IBIs. The normal model was that for clock-less devices such as thermal sensors, they would be polled vs. use an IBI since they have no clock of their own. CLK_SLOW can be a very slow clock - people use 200KHz and even 32KHz clocks for this.

Regards, Paul

On Oct 17, 2019, at 5:42 PM, Jiahua notifications@github.com<mailto:notifications@github.com> wrote:

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I use the autonomous as my top module,If my system is only scl clock,we can also use comb logic to pull down.Even we can use asm to generation this start.

Jiahua-Gong commented 5 years ago

ASM means asynchronous states machine ,It use comb logic loop to generate.It not use clock 

发自我的iPhone

------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Fri,Oct 18,2019 0:01 PM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

I am not sure what “asm” means here. But, you can generate a fake clock if you want. The CLK_SLOW is there just to synchronize the net. I agree that for a purely clock-less device which only relies on SCL, this is not generally needed, but that case is hard to see how it can work with IBIs. The normal model was that for clock-less devices such as thermal sensors, they would be polled vs. use an IBI since they have no clock of their own. CLK_SLOW can be a very slow clock - people use 200KHz and even 32KHz clocks for this.

Regards, Paul

On Oct 17, 2019, at 5:42 PM, Jiahua <notifications@github.com<mailto:notifications@github.com>> wrote:

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I use the autonomous as my top module,If my system is only scl clock,we can also use comb logic to pull down.Even we can use asm to generation this start.

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pkimelman-nxp commented 5 years ago

ASM means asynchronous states machine ,It use comb logic loop to generate.It not use clock 

OK. The problem is that we need a synchronizer normally, as a flop goes metastable if you happen to change its D input during the setup period. In your case, you would need to have the synchronizer used for IBI work with your async mechanism. You will see this wherever we cross between SCL and CLK_SLOW.

-- Paul Kimelman – Automotive Platform Architecture 408.906.9676

Jiahua-Gong commented 5 years ago

Okay,Thanks.

发自我的iPhone

------------------ Original ------------------ From: Paul Kimelman <notifications@github.com> Date: Sun,Oct 20,2019 0:24 AM To: NXP/i3c-slave-design <i3c-slave-design@noreply.github.com> Cc: Jiahua <1016765625@qq.com>, Author <author@noreply.github.com> Subject: Re: [NXP/i3c-slave-design] I3C TIMING CONTROL (#18)

ASM means asynchronous states machine ,It use comb logic loop to generate.It not use clock&nbsp;

OK. The problem is that we need a synchronizer normally, as a flop goes metastable if you happen to change its D input during the setup period. In your case, you would need to have the synchronizer used for IBI work with your async mechanism. You will see this wherever we cross between SCL and CLK_SLOW.

-- Paul Kimelman – Automotive Platform Architecture 408.906.9676

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