pkimelman-nxp
commented
5 years ago When you use RTL simulations, you have to add some logic to prevent these tiny glitches (e.g. a few ps) because the simulation Flop will trigger. No actual physical flop would, and no pad could react that fast, so this is just an artifact of the RTL sim. The normal is to make sure the connections are setup so that there is no AND or OR glitch.
Regards, Paul
On Jun 24, 2019, at 3:51 PM, juneysun notifications@github.com<mailto:notifications@github.com> wrote:
Caution: EXT Email
We have hooked up the i3c_slave with denali master. For I3C transfer, NXP I3C can get dynamic address assignment from master. However, while I3C master issues write transaction to NXP I3C slave, I3C slave detects wrong STOP bit. It breaks slave’s FSM and slave can not receive data from master. The issue is on the following code:
always @ (posedge clk_SDA or negedge rst_STOP_n) if (!rst_STOP_n) STOP_r <= 1'b0; // cannot be 1 due to any_START else if (pin_SCL_in & ~SDR_hold) // SDA rise when SCL=high STOP_r <= 1'b1; // stopped as a "state"
1). rst_STOP_n is stay as 1 2). Clk_SDA is not toggle, stay as 0 3). SDR_hold = 0 so the ~SDR_hold should have no effect in this case. 4). pin_SCL_in changing 0 -> 1 This caused the STOP_r chaning from 0 -> 1
In our case, the “i3c_sda” line is switching to tri-state. At that moment, denali model also switching from driving a weak1 to strong 0: “sda” line is also pullup on bench to a pullup strength of 1’b1. Thus it could be the glitch on SDA line causing the fake clock event. The SDA can be driven by multiple devices. Is there a way to avoid using SDA as clock? Any suggestion if this is a real issue and how to fix it?
Thanks,
June
— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHubhttps://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FNXP%2Fi3c-slave-design%2Fissues%2F8%3Femail_source%3Dnotifications%26email_token%3DAFNELX2WNAQP5LL5VMG3LELP4FFYFA5CNFSM4H3C57N2YY3PNVWWK3TUL52HS4DFUVEXG43VMWVGG33NNVSW45C7NFSM4G3NA7KQ&data=02%7C01%7Cpaul.kimelman%40nxp.com%7C3d7fe0b7ba3846ec444908d6f8f68991%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636970135081460793&sdata=%2BWdKPHGG43dOxm3D1HBil%2BgjpX46rB6Cpof9YjKnxDw%3D&reserved=0, or mute the threadhttps://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAFNELX3FZZFBXERQSWEOOJTP4FFYFANCNFSM4H3C57NQ&data=02%7C01%7Cpaul.kimelman%40nxp.com%7C3d7fe0b7ba3846ec444908d6f8f68991%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636970135081460793&sdata=oiTa4MhcBsPjeojV%2FSCHTSex2yJyLz6SI4sB7SauMek%3D&reserved=0.
-- Paul Kimelman – Automotive Platform Architecture 408.906.9676
We have hooked up the i3c_slave with denali master. For I3C transfer, NXP I3C can get dynamic address assignment from master. However, while I3C master issues write transaction to NXP I3C slave, I3C slave detects wrong STOP bit. It breaks slave’s FSM and slave can not receive data from master. The issue is on the following code:
always @ (posedge clk_SDA or negedge rst_STOP_n) if (!rst_STOP_n) STOP_r <= 1'b0; // cannot be 1 due to any_START else if (pin_SCL_in & ~SDR_hold) // SDA rise when SCL=high STOP_r <= 1'b1; // stopped as a "state"
1). rst_STOP_n is stay as 1 2). Clk_SDA is not toggle, stay as 0 3). SDR_hold = 0 so the ~SDR_hold should have no effect in this case. 4). pin_SCL_in changing 0 -> 1 This caused the STOP_r chaning from 0 -> 1
In our case, the “i3c_sda” line is switching to tri-state. At that moment, denali model also switching from driving a weak1 to strong 0: “sda” line is also pullup on bench to a pullup strength of 1’b1. Thus it could be the glitch on SDA line causing the fake clock event. The SDA can be driven by multiple devices. Is there a way to avoid using SDA as clock? Any suggestion if this is a real issue and how to fix it?
Thanks,
June