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NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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Module: CSR Counters and Registers #102

Closed ShinyMiraidon closed 9 months ago

ShinyMiraidon commented 10 months ago

CSR Counters and Registers Outline

ShinyMiraidon commented 10 months ago

Specifics of the CSR Counters and Registers are covered in Section 2.8 of the RISCV Unprivileged Spec V2.2 and Chapter 2 of the RISCV Privileged Spec V1.12

ShinyMiraidon commented 9 months ago

Not going to be implemented as uneeded in base instruction set