The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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interfaces(MEM.sv, DCache_Manager_Control.sv, Branch_Manager_Input.sv, Alu_Ops.sv, DReg_Info.sv, SReg_Nums.sv): Added Various Interfaces #120
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ShinyMiraidon closed 9 months ago
Added the following interfaces: