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NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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update docs(10_L1_Data_Cache.md, 03_L1_Data_Cache.md), rtl(L1_Data_Ca… #139

Closed suriyasaiyan closed 5 months ago

suriyasaiyan commented 7 months ago

…che.sv), dv(sVerilogTests, L1_Data_Cache.sv))

codecov[bot] commented 7 months ago

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Comparison is base (b1d7981) 96.69% compared to head (098bfdf) 96.69%.

Additional details and impacted files ```diff @@ Coverage Diff @@ ## main #139 +/- ## ======================================= Coverage 96.69% 96.69% ======================================= Files 12 12 Lines 212 212 ======================================= Hits 205 205 Misses 7 7 ```

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ShinyMiraidon commented 7 months ago

Everything looks good so far. Do you want me to merge this pull request now or wait for the L2 cache and other things to be added?

suriyasaiyan commented 7 months ago

i am fine either way, i can PR after L2. i will complete it in the holidays

ShinyMiraidon commented 7 months ago

I'll wait to merge until L2 is added. That way I can review everything at once, especially since you're using test benches and not Verilator tests