module(l1_data_cache): Added test and fixed issues with module

NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.

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module(l1_data_cache): Added test and fixed issues with module #165

Closed ShinyMiraidon closed 2 months ago

ShinyMiraidon commented 3 months ago

This PR is not yet ready to merge as there is still a lot of work that needs to be done with the l1 data cache and its test. Just using this PR at the moment to troubleshoot some issues I'm having with running tests.