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NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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Module: L3 Data Cache #24

Open ShinyMiraidon opened 1 year ago

ShinyMiraidon commented 1 year ago

L3 Data Cache Outline

L3 Data Cache Structure Overview

ShinyMiraidon commented 1 year ago

Make sure to communicate with the Memory team as well as those working on other cache levels to ensure compatibility

ShinyMiraidon commented 10 months ago

L3 Data Cache is currently on hold as not needed for core functionality