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NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
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Connection Module: Instruction Cache #94

Open ShinyMiraidon opened 10 months ago

ShinyMiraidon commented 10 months ago

Instruction Cache Outline

ShinyMiraidon commented 7 months ago

Connection module that will be the top-level module for communicating with the Instruction Cache. Should include the Instruction Cache Manager and L1 Instruction Cache Modules.