urjtag.error: out of bounds: register length 1 mismatch: 1080

[richardklingler]

Clicking "Shift DR" causes an error with:

Traceback (most recent call last): File "/home/klingler/develop/jtagGUI/Panels/LeftPanel.py", line 154, in shiftDR self.mainW.shiftDR(event) File "/home/klingler/develop/jtagGUI/Panels/MainWindow.py", line 256, in shiftDR self.chain.set_dr_in(in_bsr[1]) urjtag.error: out of bounds: register length 1 mismatch: 1080

Probably the reason I can't set any pin states in Debian 11.1.

[Najsztub]

Hi, unfortunately I don't have this device at my disposal. I've tried using the second device BSDL file from bsdl.info. I've been trying to debug the mock DUT using randomly generated BSR values.

By default the instruction is set to BYPASS. If you want to view and set the pins, you should set the IR to SAMPLE.

You can do this by double clicking on the SAMPLE instruction. The instruction is ready to be loaded into the IR (which is indicated by the '<' mark). You then shift the instruction by clicking the 'Shift IR' button (also with '<' indicating that an instruction is ready to be loaded). You should be able to access the BSR register now, showing pin status.

This is how it should look:

Let me know if this helped.

Best, Mateusz

[richardklingler]

Hi Mateusz

Great to know this project is active as it seems to be the only one available for Linux :-)

Okay...think I got it now to the point it can read the pin states...but only those from the FPGA design, a simple counter, are toggling...all other pins are showing as '1', regardless if I pull them low or high....also setting a pin state does nothing....

Not sure if Cyclone IV is doing something different here...gonna check now a Spartan-6 board....one of those cheapo HUB75 LED panel driver boards where I have to reverse engineer the pin mapping...

[Najsztub]

Thanks for the kind words! I appreciate it.

Try setting the IR into EXTEST, set the pins and issue 'Shitf DR'.

[richardklingler]

That works on my 20 years old EP1C3 PacMan board (o;

Seems EP4CE15 behaves differently with EXTEST as it does nothing.....or the QMTech board documentation is totally wrong (o;

BTW: A color legend under or above the chip outline would be nice...still don't know what all those colors and backgrounds mean....

cheers richard

[richardklingler]

Okay..closing this one...but gonna do a new one..sorry (o;