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NationalSecurityAgency / ghidra

Ghidra is a software reverse engineering (SRE) framework
https://www.nsa.gov/ghidra
Apache License 2.0
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PowerPC VLE Floating-Point support #434

Closed arkup closed 5 years ago

arkup commented 5 years ago

Describe the bug Hi, would be great if you implement PowerPC VLE floating-point instructions support. Seems only IDA, objdump can disasm the FPU instructions.

To Reproduce

Create a file with the data 10 60 02 D1 13 a3 02 c9 open as PowerPC VLE

Language ID:    PowerPC:BE:64:VLEALT-32addr (1.5)
Processor:  PowerPC
Endian: Big
Address Size:   32

Expected behavior

10 60 02 D1      efscfsi   r3, r0
13 a3 02 c9      efsdiv  r29,r3,r0

Environment:

mumbel commented 5 years ago

These look like bugs in Scalar_SPFP.sinc

Change OP=4 to 1 in efscfsi Change OP=4 to 9 in efsdiv

Seems most of them are copy paste bugged. oops, @ghidra1 sorry for not checking that better

ghidra1 commented 5 years ago

"OP" is a 6-bit field so the existing patterns are correct.

See comments at end of ppc_64_isa_altivec_vle_be.slaspec

Unfortunately Ghidra does not separate all the valid combinations of PowerPC feature sets (EVX vs. Altivec). The presence of Altivec support which is enabled in this variant by default precludes the presence of EVX. We already have 19 variants of PPC, many more variants would be required to handle the various combinations not yet. This is very hidden and certainly could use some attention.

You can try un-commenting the EVX support and comment-out the Altivec include. Restart Ghidra and try again.

arkup commented 5 years ago

You can try un-commenting the EVX support and comment-out the Altivec include. Restart Ghidra and try again.

exactly right, works now thanks @ghidra1 !