x86: Add constraint to mod field of instructions that can only encode registers

[Sleigh-InSPECtor]

The 0fc5 encoding for PEXTRW can only encode register values so ModRM.mod must be equal to 3. Currently, the SLEIGH specification just ignores the ModRM.mod field when decoding PEXTRW, however any case where ModRM.mod!=1 should be treated as invalid instruction. The same thing is also true for the MOVQ2DQ instruction.

This PR adds the additional constraint to the PEXTRW and MOVQ2DQ constructors.

e.g.,

• 0fc50000 (mod=0b00), 0fc54000 (mod=0b01), 0fc58000 (mod=0b10):

  • Hardware Reference (AMD CPU & Intel CPU): #UD (Invalid Opcode Exception)
  • x86:LE:64:default (Existing): "PEXTRW EAX, MM0, 0x0"
  • x86:LE:64:default (This patch): (Invalid)

• 0fc5c000 (mod=0b11) with MM0=1

  • Hardware Reference (AMD CPU & Intel CPU): { RAX=1 }
  • x86:LE:64:default (Unchanged): "PEXTRW EAX, MM0, 0x0" { RAX=1 }

• f30fd600 (mod=0b00), f30fd640 (mod=0b01), f30fd680 (mod=0b10):

  • Hardware Reference (AMD CPU & Intel CPU): #UD (Invalid Opcode Exception)
  • x86:LE:64:default (Existing): "MOVQ2DQ XMM0, MM0"
  • x86:LE:64:default (This patch): (Invalid)