As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the rmif instruction for AARCH64. According to Section C6.2.260, the expected behaviour is to rotate right the value in the operand register, and the lower bits are copied into the NZCV flags. While the current behaviour instead performs a right shift, clearing some bits when the shift immediate is greater than 60.
e.g.:
0xcf871fba "rmif x30, #0x3f, #0xf" with x30 = 0x5f6d9d6c85ec78e5
As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the rmif instruction for AARCH64. According to Section C6.2.260, the expected behaviour is to rotate right the value in the operand register, and the lower bits are copied into the NZCV flags. While the current behaviour instead performs a right shift, clearing some bits when the shift immediate is greater than 60.
e.g.:
0xcf871fba"rmif x30, #0x3f, #0xf" with x30 = 0x5f6d9d6c85ec78e5Hardware Reference: NZCV = 0xa Existing Spec: NZCV = 0x0 Patched Spec: NZCV = 0xa