Marc-Bender
commented
4 years ago xor with a mask where only the MSB is set is not quite the same as negating (see twos-complement)
Open NWPlayer123 opened 5 years ago
Marc-Bender
commented
4 years ago xor with a mask where only the MSB is set is not quite the same as negating (see twos-complement)
Is your feature request related to a problem? Please describe. 32-bit C/++ compilers can do 64-bit types e.g. doubles and u/longlong, obviously, but it has to do all these combination instructions, which confuses Ghidra's decomp.
Additional context here's a couple examples: see: 10th line from the bottom with BusClockSpeed, it's obviously a 64-bit value, but it treats it as two separate registers, e.g. uVar3+uVar4 A solution would be to let the user highlight two variables (those two lines), right click, and merge...somehow
```c long __CARDStart(long chan,CARDCallback tx_cb,CARDCallback exi_cb) { byte bVar1; bool_t level; long ret; int iVar2; uint uVar3; uint uVar4; long error; level = OSDisableInterrupts(); if (__CARDBlock[chan].attached == 0) { error = -3; goto LAB_00010fbc; } if (tx_cb != NULL) { __CARDBlock[chan].tx_cb = tx_cb; } if (exi_cb != NULL) { __CARDBlock[chan].exi_cb = exi_cb; } __CARDBlock[chan].unlock_cb = UnlockedCallback; ret = EXILock(chan,0,__CARDUnlockedHandler); if (ret == 0) { error = -1; goto LAB_00010fbc; } __CARDBlock[chan].unlock_cb = NULL; iVar2 = EXISelect(chan,0,4); if (iVar2 == 0) { EXIUnlock(chan); error = -3; goto LAB_00010fbc; } OSCancelAlarm(chan * 0x110 + 0x11d30); bVar1 = *(byte *)&__CARDBlock[chan].field_0x94; if (bVar1 != 0xf3) { if (bVar1 < 0xf3) { if (bVar1 == 0xf1) { LAB_00010f54: uVar3 = __CARDBlock[chan].field_0xc; uVar4 = (BusClockSpeed >> 2) * 2; uVar3 = ((int)uVar3 >> 0xd) + (uint)((int)uVar3 < 0 && (uVar3 & 0x1fff) != 0); OSSetAlarm(&__CARDBlock[chan].alarm,CONCAT44(((int)uVar3 >> 0x1f) * uVar4 + (int)((ulonglong)uVar3 * (ulonglong)uVar4 >> 0x20),uVar3 * uVar4),TimeoutHandler); } else { if (0xf0 < bVar1) { OSSetAlarm(&__CARDBlock[chan].alarm,(ulonglong)(((BusClockSpeed >> 2) / 1000) * 100),TimeoutHandler); } } } else { if (bVar1 < 0xf5) { if (*(ushort *)((int)&__CARDBlock[chan].field_0x8 + 2) < 0x81) goto LAB_00010f54; uVar4 = (int)(uint)*(ushort *)&__CARDBlock[chan].field_0x10 >> 6; uVar3 = (BusClockSpeed >> 2) * 2; OSSetAlarm(&__CARDBlock[chan].alarm,(ulonglong)uVar4 * (ulonglong)uVar3 & 0xffffffff00000000 | (ulonglong)(uVar4 * uVar3),TimeoutHandler); } } } error = 0; LAB_00010fbc: OSRestoreInterrupts(level); return error; } ``` from ``` ************************************************************** * FUNCTION ************************************************************** long __stdcall __CARDStart (long chan, CARDCallback tx_cb long r3:4
long r3:4 chan XREF[1]: 00010e34 (W)
CARDCallback r4:4 tx_cb
CARDCallback r5:4 exi_cb
long r29:4 error XREF[1]: 00010df8 (W)
long r3:4 ret XREF[1]: 00010e34 (W)
undefined4 Stack[0x4]:4 local_res4 XREF[2]: [more]
undefined4 Stack[-0x14]:4 local_14 XREF[2]: [more]
undefined4 Stack[-0x30]:4 local_30 XREF[1]: 00010dc0 (W)
__CARDStart XREF[4]: 00011058 (c), [more]
00010db8 7c 08 02 a6 mfspr r0,LR
r0 = COPY LR
00010dbc 90 01 00 04 stw r0,local_res4 (r1)
$U1750 :4 = INT_ADD r1, 4:4
STORE ram($U1750 ), r0
00010dc0 94 21 ff d0 stwu r1,local_30 (r1)
$U1790 :4 = INT_ADD r1, 0xffffffd0 :4
STORE ram($U1790 ), r1
r1 = COPY $U1790
00010dc4 bf 61 00 1c stmw r27,local_14 (r1)
$U1750 :4 = INT_ADD r1, 28:4
tea = COPY $U1750
STORE ram(tea), r27
tea = INT_ADD tea, 4:4
STORE ram(tea), r28
tea = INT_ADD tea, 4:4
STORE ram(tea), r29
tea = INT_ADD tea, 4:4
STORE ram(tea), r30
tea = INT_ADD tea, 4:4
STORE ram(tea), r31
tea = INT_ADD tea, 4:4
00010dc8 3b 63 00 00 addi r27,chan,0x0
r27 = INT_ADD r3, 0:4
00010dcc 3b 84 00 00 addi r28,tx_cb,0x0
r28 = INT_ADD r4, 0:4
00010dd0 3b a5 00 00 addi r29,exi_cb ,0x0
r29 = INT_ADD r5, 0:4
00010dd4 48 00 12 61 bl OSDisableInterrupts bool_t OSDisableInterrupts(void)
r2Save = COPY r2
LR = COPY 0x10dd8 :4
CALL *[ram]0x12034 :4
00010dd8 1c bb 01 10 mulli exi_cb ,r27,0x110
r5 = INT_MULT r27, 0x110:4
00010ddc 3c 80 00 01 lis tx_cb,0x1
r4 = INT_LEFT 1:4, 16:4
00010de0 38 04 1c 50 addi r0,tx_cb,0x1c50
r0 = INT_ADD r4, 0x1c50 :4
00010de4 7f e0 2a 14 add r31,r0,exi_cb
r31 = INT_ADD r0, r5
00010de8 80 1f 00 00 lwz r0=>__CARDBlock ,0x0(r31) =
$U1750 :4 = INT_ADD r31, 0:4
r0 = LOAD ram($U1750 )
00010dec 3b c3 00 00 addi r30,chan,0x0
r30 = INT_ADD r3, 0:4
00010df0 2c 00 00 00 cmpwi r0,0x0
$U2780 :4 = COPY r0
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010df4 40 82 00 0c bne LAB_00010e00
$U1480 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1480 :1 = INT_AND $U120, 1:1
$U1480 :1 = BOOL_NEGATE $U1480
CBRANCH *[ram]0x10e00 :4, $U1480
00010df8 3b a0 ff fd li error,-0x3
r29 = COPY 0xfffffffd :4
00010dfc 48 00 01 c0 b LAB_00010fbc
BRANCH *[ram]0x10fbc :4
LAB_00010e00 XREF[1]: 00010df4 (j)
00010e00 28 1c 00 00 cmplwi r28,0x0
$U2a80 :4 = COPY r28
$U2a90 :4 = COPY 0:4
$U2aa0 :1 = INT_LESS $U2a80 , $U2a90
$U2ab0 :1 = INT_LEFT $U2aa0 , 3:4
$U2ac0 :1 = INT_LESS $U2a90 , $U2a80
$U2ad0 :1 = INT_LEFT $U2ac0 , 2:4
$U2ae0 :1 = INT_OR $U2ab0 , $U2ad0
$U2af0 :1 = INT_EQUAL $U2a80 , $U2a90
$U2b00 :1 = INT_LEFT $U2af0 , 1:4
$U2b10 :1 = INT_OR $U2ae0 , $U2b00
$U2b20 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2b10 , $U2b20
00010e04 41 82 00 08 beq LAB_00010e0c
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x10e0c :4, $U1440
00010e08 93 9f 00 c8 stw r28,0xc8(r31)=>__CARDBlock[0].tx_cb = null
$U1750 :4 = INT_ADD r31, 0xc8:4
STORE ram($U1750 ), r28
LAB_00010e0c XREF[1]: 00010e04 (j)
00010e0c 28 1d 00 00 cmplwi error,0x0
$U2a80 :4 = COPY r29
$U2a90 :4 = COPY 0:4
$U2aa0 :1 = INT_LESS $U2a80 , $U2a90
$U2ab0 :1 = INT_LEFT $U2aa0 , 3:4
$U2ac0 :1 = INT_LESS $U2a90 , $U2a80
$U2ad0 :1 = INT_LEFT $U2ac0 , 2:4
$U2ae0 :1 = INT_OR $U2ab0 , $U2ad0
$U2af0 :1 = INT_EQUAL $U2a80 , $U2a90
$U2b00 :1 = INT_LEFT $U2af0 , 1:4
$U2b10 :1 = INT_OR $U2ae0 , $U2b00
$U2b20 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2b10 , $U2b20
00010e10 41 82 00 08 beq LAB_00010e18
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x10e18 :4, $U1440
00010e14 93 bf 00 cc stw error,0xcc(r31)=>__CARDBlock[0].exi_cb = null
$U1750 :4 = INT_ADD r31, 0xcc:4
STORE ram($U1750 ), r29
LAB_00010e18 XREF[1]: 00010e10 (j)
00010e18 3c 60 00 01 lis chan,0x1
r3 = INT_LEFT 1:4, 16:4
00010e1c 38 03 0c a8 addi r0,chan,0xca8
r0 = INT_ADD r3, 0xca8:4
00010e20 3c 60 00 01 lis chan,0x1
r3 = INT_LEFT 1:4, 16:4
00010e24 90 1f 00 dc stw r0=>UnlockedCallback ,0xdc(r31)=>__CARDBlock[0] = null
$U1750 :4 = INT_ADD r31, 0xdc:4
STORE ram($U1750 ), r0
00010e28 38 a3 02 d0 addi exi_cb =>__CARDUnlockedHandler ,chan,0x2d0
r5 = INT_ADD r3, 0x2d0:4
00010e2c 38 7b 00 00 addi chan,r27,0x0
r3 = INT_ADD r27, 0:4
00010e30 38 80 00 00 li tx_cb,0x0
r4 = COPY 0:4
00010e34 48 00 11 d9 bl EXILock long EXILock(long chan, long dev
r2Save = COPY r2
LR = COPY 0x10e38 :4
CALL *[ram]0x1200c :4
00010e38 2c 03 00 00 cmpwi ret,0x0
$U2780 :4 = COPY r3
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010e3c 40 82 00 0c bne LAB_00010e48
$U1480 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1480 :1 = INT_AND $U120, 1:1
$U1480 :1 = BOOL_NEGATE $U1480
CBRANCH *[ram]0x10e48 :4, $U1480
00010e40 3b a0 ff ff li error,-0x1
r29 = COPY 0xffffffff :4
00010e44 48 00 01 78 b LAB_00010fbc
BRANCH *[ram]0x10fbc :4
LAB_00010e48 XREF[1]: 00010e3c (j)
00010e48 3b a0 00 00 li error,0x0
r29 = COPY 0:4
00010e4c 93 bf 00 dc stw error,0xdc(r31)=>__CARDBlock[0].unlock_cb = null
$U1750 :4 = INT_ADD r31, 0xdc:4
STORE ram($U1750 ), r29
00010e50 38 7b 00 00 addi ret,r27,0x0
r3 = INT_ADD r27, 0:4
00010e54 38 80 00 00 li tx_cb,0x0
r4 = COPY 0:4
00010e58 38 a0 00 04 li exi_cb ,0x4
r5 = COPY 4:4
00010e5c 48 00 11 c1 bl EXISelect undefined EXISelect()
r2Save = COPY r2
LR = COPY 0x10e60 :4
CALL *[ram]0x1201c :4
00010e60 2c 03 00 00 cmpwi ret,0x0
$U2780 :4 = COPY r3
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010e64 40 82 00 14 bne LAB_00010e78
$U1480 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1480 :1 = INT_AND $U120, 1:1
$U1480 :1 = BOOL_NEGATE $U1480
CBRANCH *[ram]0x10e78 :4, $U1480
00010e68 7f 63 db 78 or ret,r27,r27
r3 = INT_OR r27, r27
00010e6c 48 00 11 a5 bl EXIUnlock undefined EXIUnlock()
r2Save = COPY r2
LR = COPY 0x10e70 :4
CALL *[ram]0x12010 :4
00010e70 3b a0 ff fd li error,-0x3
r29 = COPY 0xfffffffd :4
00010e74 48 00 01 48 b LAB_00010fbc
BRANCH *[ram]0x10fbc :4
LAB_00010e78 XREF[1]: 00010e64 (j)
00010e78 38 7f 00 e0 addi ret,r31,0xe0
r3 = INT_ADD r31, 0xe0:4
00010e7c 48 00 11 8d bl OSCancelAlarm undefined OSCancelAlarm()
r2Save = COPY r2
LR = COPY 0x10e80 :4
CALL *[ram]0x12008 :4
00010e80 88 1f 00 94 lbz r0,0x94(r31)=>__CARDBlock[0].field_0x94 = null
$U1750 :4 = INT_ADD r31, 0x94:4
$U47a0 :1 = LOAD ram($U1750 )
r0 = INT_ZEXT $U47a0
00010e84 2c 00 00 f3 cmpwi r0,0xf3
$U2780 :4 = COPY r0
$U2790 :4 = COPY 0xf3:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010e88 41 82 01 30 beq LAB_00010fb8
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x10fb8 :4, $U1440
00010e8c 40 80 00 14 bge LAB_00010ea0
$U1450 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 0:4
$U120:1 = INT_RIGHT cr0, $U100
$U1450 :1 = INT_AND $U120, 1:1
$U1450 :1 = BOOL_NEGATE $U1450
CBRANCH *[ram]0x10ea0 :4, $U1450
00010e90 2c 00 00 f1 cmpwi r0,0xf1
$U2780 :4 = COPY r0
$U2790 :4 = COPY 0xf1:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010e94 41 82 00 c0 beq LAB_00010f54
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x10f54 :4, $U1440
00010e98 40 80 00 14 bge LAB_00010eac
$U1450 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 0:4
$U120:1 = INT_RIGHT cr0, $U100
$U1450 :1 = INT_AND $U120, 1:1
$U1450 :1 = BOOL_NEGATE $U1450
CBRANCH *[ram]0x10eac :4, $U1450
00010e9c 48 00 01 1c b LAB_00010fb8
BRANCH *[ram]0x10fb8 :4
LAB_00010ea0 XREF[1]: 00010e8c (j)
00010ea0 2c 00 00 f5 cmpwi r0,0xf5
$U2780 :4 = COPY r0
$U2790 :4 = COPY 0xf5:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00010ea4 40 80 01 14 bge LAB_00010fb8
$U1450 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 0:4
$U120:1 = INT_RIGHT cr0, $U100
$U1450 :1 = INT_AND $U120, 1:1
$U1450 :1 = BOOL_NEGATE $U1450
CBRANCH *[ram]0x10fb8 :4, $U1450
00010ea8 48 00 00 3c b LAB_00010ee4
BRANCH *[ram]0x10ee4 :4
LAB_00010eac XREF[1]: 00010e98 (j)
00010eac 3c 60 80 00 lis ret,-0x8000
r3 = INT_LEFT 0xffff8000 :4, 16:4
00010eb0 80 03 00 f8 lwz r0,offset BusClockSpeed (ret) = 9A7EC80h
$U1750 :4 = INT_ADD r3, 0xf8:4
r0 = LOAD ram($U1750 )
00010eb4 3c 80 10 62 lis tx_cb,0x1062
r4 = INT_LEFT 0x1062 :4, 16:4
00010eb8 3c 60 00 01 lis ret,0x1
r3 = INT_LEFT 1:4, 16:4
00010ebc 54 00 f0 be rlwinm r0,r0,0x1e,0x2,0x1f
$U6770 :1 = COPY 30:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0x3fffffff :4
00010ec0 38 84 4d d3 addi tx_cb,tx_cb,0x4dd3
r4 = INT_ADD r4, 0x4dd3 :4
00010ec4 7c 04 00 16 mulhwu r0,tx_cb,r0
$U6370 :8 = INT_ZEXT r4
$U6380 :8 = INT_ZEXT r0
$U63a0 :8 = INT_MULT $U6370 , $U6380
r0 = SUBPIECE $U63a0 , 4:4
00010ec8 54 00 d1 be rlwinm r0,r0,0x1a,0x6,0x1f
$U6770 :1 = COPY 26:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0x3ffffff :4
00010ecc 1c c0 00 64 mulli r6,r0,0x64
r6 = INT_MULT r0, 0x64:4
00010ed0 38 e3 07 f8 addi r7=>TimeoutHandler ,ret,0x7f8
r7 = INT_ADD r3, 0x7f8:4
00010ed4 38 7f 00 e0 addi ret,r31,0xe0
r3 = INT_ADD r31, 0xe0:4
00010ed8 38 a0 00 00 li exi_cb ,0x0
r5 = COPY 0:4
00010edc 48 00 11 4d bl OSSetAlarm void OSSetAlarm(OSAlarm * alarm,
r2Save = COPY r2
LR = COPY 0x10ee0 :4
CALL *[ram]0x12028 :4
00010ee0 48 00 00 d8 b LAB_00010fb8
BRANCH *[ram]0x10fb8 :4
LAB_00010ee4 XREF[1]: 00010ea8 (j)
00010ee4 a0 1f 00 0a lhz r0,0xa(r31)=>__CARDBlock[0].field_0x8+2 = null
$U1750 :4 = INT_ADD r31, 10:4
$U4a90 :2 = LOAD ram($U1750 )
r0 = INT_ZEXT $U4a90
00010ee8 28 00 00 80 cmplwi r0,0x80
$U2a80 :4 = COPY r0
$U2a90 :4 = COPY 0x80:4
$U2aa0 :1 = INT_LESS $U2a80 , $U2a90
$U2ab0 :1 = INT_LEFT $U2aa0 , 3:4
$U2ac0 :1 = INT_LESS $U2a90 , $U2a80
$U2ad0 :1 = INT_LEFT $U2ac0 , 2:4
$U2ae0 :1 = INT_OR $U2ab0 , $U2ad0
$U2af0 :1 = INT_EQUAL $U2a80 , $U2a90
$U2b00 :1 = INT_LEFT $U2af0 , 1:4
$U2b10 :1 = INT_OR $U2ae0 , $U2b00
$U2b20 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2b10 , $U2b20
00010eec 40 81 00 68 ble LAB_00010f54
$U1420 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 1:4
$U120:1 = INT_RIGHT cr0, $U100
$U1420 :1 = INT_AND $U120, 1:1
$U1420 :1 = BOOL_NEGATE $U1420
CBRANCH *[ram]0x10f54 :4, $U1420
00010ef0 3c 60 80 00 lis ret,-0x8000
r3 = INT_LEFT 0xffff8000 :4, 16:4
00010ef4 a0 9f 00 10 lhz tx_cb,0x10(r31)=>__CARDBlock[0].field_0x10 = null
$U1750 :4 = INT_ADD r31, 16:4
$U4a90 :2 = LOAD ram($U1750 )
r4 = INT_ZEXT $U4a90
00010ef8 80 63 00 f8 lwz ret,offset BusClockSpeed (ret) = 9A7EC80h
$U1750 :4 = INT_ADD r3, 0xf8:4
r3 = LOAD ram($U1750 )
00010efc 38 00 00 02 li r0,0x2
r0 = COPY 2:4
00010f00 7c 89 36 70 srawi r9,tx_cb,0x6
$U90:4 = COPY r4
$Ua0:4 = INT_LEFT 1:4, 6:4
$U90:4 = INT_SUB $Ua0, 1:4
$Uc0:1 = INT_SLESS r4, 0:4
$Ud0:4 = INT_AND r4, $U90
$Ue0:1 = INT_NOTEQUAL $Ud0, 0:4
xer_ca = BOOL_AND $Uc0, $Ue0
r9 = INT_SRIGHT r4, 6:4
00010f04 54 63 f0 be rlwinm ret,ret,0x1e,0x2,0x1f
$U6770 :1 = COPY 30:1
$U6780 :4 = INT_LEFT r3, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r3, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r3 = INT_AND $U67c0 , 0x3fffffff :4
00010f08 7d 1d 01 d6 mullw r8,error,r0
r8 = INT_MULT r29, r0
00010f0c 7c c3 00 16 mulhwu r6,ret,r0
$U6370 :8 = INT_ZEXT r3
$U6380 :8 = INT_ZEXT r0
$U63a0 :8 = INT_MULT $U6370 , $U6380
r6 = SUBPIECE $U63a0 , 4:4
00010f10 7d 08 32 14 add r8,r8,r6
r8 = INT_ADD r8, r6
00010f14 7c a3 01 d6 mullw exi_cb ,ret,r0
r5 = INT_MULT r3, r0
00010f18 7d 29 01 94 addze r9,r9
$U21c0 :4 = INT_ZEXT xer_ca
xer_ca = INT_CARRY r9, $U21c0
r9 = INT_ADD r9, $U21c0
00010f1c 7d 20 fe 70 srawi r0,r9,0x1f
$U90:4 = COPY r9
$Ua0:4 = INT_LEFT 1:4, 31:4
$U90:4 = INT_SUB $Ua0, 1:4
$Uc0:1 = INT_SLESS r9, 0:4
$Ud0:4 = INT_AND r9, $U90
$Ue0:1 = INT_NOTEQUAL $Ud0, 0:4
xer_ca = BOOL_AND $Uc0, $Ue0
r0 = INT_SRIGHT r9, 31:4
00010f20 7c c3 e9 d6 mullw r6,ret,error
r6 = INT_MULT r3, r29
00010f24 7c 80 29 d6 mullw tx_cb,r0,exi_cb
r4 = INT_MULT r0, r5
00010f28 7c 09 28 16 mulhwu r0,r9,exi_cb
$U6370 :8 = INT_ZEXT r9
$U6380 :8 = INT_ZEXT r5
$U63a0 :8 = INT_MULT $U6370 , $U6380
r0 = SUBPIECE $U63a0 , 4:4
00010f2c 3c 60 00 01 lis ret,0x1
r3 = INT_LEFT 1:4, 16:4
00010f30 38 e3 07 f8 addi r7=>TimeoutHandler ,ret,0x7f8
r7 = INT_ADD r3, 0x7f8:4
00010f34 7c 68 32 14 add ret,r8,r6
r3 = INT_ADD r8, r6
00010f38 7c 84 02 14 add tx_cb,tx_cb,r0
r4 = INT_ADD r4, r0
00010f3c 7c 09 19 d6 mullw r0,r9,ret
r0 = INT_MULT r9, r3
00010f40 7c c9 29 d6 mullw r6,r9,exi_cb
r6 = INT_MULT r9, r5
00010f44 38 7f 00 e0 addi ret,r31,0xe0
r3 = INT_ADD r31, 0xe0:4
00010f48 7c a4 02 14 add exi_cb ,tx_cb,r0
r5 = INT_ADD r4, r0
00010f4c 48 00 10 dd bl OSSetAlarm void OSSetAlarm(OSAlarm * alarm,
r2Save = COPY r2
LR = COPY 0x10f50 :4
CALL *[ram]0x12028 :4
00010f50 48 00 00 68 b LAB_00010fb8
BRANCH *[ram]0x10fb8 :4
LAB_00010f54 XREF[2]: 00010e94 (j), [more]
00010f54 3c 60 80 00 lis ret,-0x8000
r3 = INT_LEFT 0xffff8000 :4, 16:4
00010f58 80 9f 00 0c lwz tx_cb,0xc(r31)=>__CARDBlock[0].field_0xc = null
$U1750 :4 = INT_ADD r31, 12:4
r4 = LOAD ram($U1750 )
00010f5c 80 03 00 f8 lwz r0,offset BusClockSpeed (ret) = 9A7EC80h
$U1750 :4 = INT_ADD r3, 0xf8:4
r0 = LOAD ram($U1750 )
00010f60 3c 60 00 01 lis ret,0x1
r3 = INT_LEFT 1:4, 16:4
00010f64 7c 89 6e 70 srawi r9,tx_cb,0xd
$U90:4 = COPY r4
$Ua0:4 = INT_LEFT 1:4, 13:4
$U90:4 = INT_SUB $Ua0, 1:4
$Uc0:1 = INT_SLESS r4, 0:4
$Ud0:4 = INT_AND r4, $U90
$Ue0:1 = INT_NOTEQUAL $Ud0, 0:4
xer_ca = BOOL_AND $Uc0, $Ue0
r9 = INT_SRIGHT r4, 13:4
00010f68 54 07 f0 be rlwinm r7,r0,0x1e,0x2,0x1f
$U6770 :1 = COPY 30:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r7 = INT_AND $U67c0 , 0x3fffffff :4
00010f6c 38 00 00 02 li r0,0x2
r0 = COPY 2:4
00010f70 38 80 00 00 li tx_cb,0x0
r4 = COPY 0:4
00010f74 7d 04 01 d6 mullw r8,tx_cb,r0
r8 = INT_MULT r4, r0
00010f78 7c c7 00 16 mulhwu r6,r7,r0
$U6370 :8 = INT_ZEXT r7
$U6380 :8 = INT_ZEXT r0
$U63a0 :8 = INT_MULT $U6370 , $U6380
r6 = SUBPIECE $U63a0 , 4:4
00010f7c 7d 08 32 14 add r8,r8,r6
r8 = INT_ADD r8, r6
00010f80 7c a7 01 d6 mullw exi_cb ,r7,r0
r5 = INT_MULT r7, r0
00010f84 7d 29 01 94 addze r9,r9
$U21c0 :4 = INT_ZEXT xer_ca
xer_ca = INT_CARRY r9, $U21c0
r9 = INT_ADD r9, $U21c0
00010f88 7c c7 21 d6 mullw r6,r7,tx_cb
r6 = INT_MULT r7, r4
00010f8c 7d 20 fe 70 srawi r0,r9,0x1f
$U90:4 = COPY r9
$Ua0:4 = INT_LEFT 1:4, 31:4
$U90:4 = INT_SUB $Ua0, 1:4
$Uc0:1 = INT_SLESS r9, 0:4
$Ud0:4 = INT_AND r9, $U90
$Ue0:1 = INT_NOTEQUAL $Ud0, 0:4
xer_ca = BOOL_AND $Uc0, $Ue0
r0 = INT_SRIGHT r9, 31:4
00010f90 7c 80 29 d6 mullw tx_cb,r0,exi_cb
r4 = INT_MULT r0, r5
00010f94 7c 09 28 16 mulhwu r0,r9,exi_cb
$U6370 :8 = INT_ZEXT r9
$U6380 :8 = INT_ZEXT r5
$U63a0 :8 = INT_MULT $U6370 , $U6380
r0 = SUBPIECE $U63a0 , 4:4
00010f98 38 e3 07 f8 addi r7=>TimeoutHandler ,ret,0x7f8
r7 = INT_ADD r3, 0x7f8:4
00010f9c 7c 68 32 14 add ret,r8,r6
r3 = INT_ADD r8, r6
00010fa0 7c 84 02 14 add tx_cb,tx_cb,r0
r4 = INT_ADD r4, r0
00010fa4 7c 09 19 d6 mullw r0,r9,ret
r0 = INT_MULT r9, r3
00010fa8 7c c9 29 d6 mullw r6,r9,exi_cb
r6 = INT_MULT r9, r5
00010fac 38 7f 00 e0 addi ret,r31,0xe0
r3 = INT_ADD r31, 0xe0:4
00010fb0 7c a4 02 14 add exi_cb ,tx_cb,r0
r5 = INT_ADD r4, r0
00010fb4 48 00 10 75 bl OSSetAlarm void OSSetAlarm(OSAlarm * alarm,
r2Save = COPY r2
LR = COPY 0x10fb8 :4
CALL *[ram]0x12028 :4
LAB_00010fb8 XREF[5]: 00010e88 (j), [more]
00010fb8 3b a0 00 00 li error,0x0
r29 = COPY 0:4
LAB_00010fbc XREF[3]: 00010dfc (j), [more]
00010fbc 7f c3 f3 78 or ret,r30,r30
r3 = INT_OR r30, r30
00010fc0 48 00 10 79 bl OSRestoreInterrupts bool_t OSRestoreInterrupts(bool_
r2Save = COPY r2
LR = COPY 0x10fc4 :4
CALL *[ram]0x12038 :4
00010fc4 7f a3 eb 78 or ret,error,error
r3 = INT_OR r29, r29
00010fc8 bb 61 00 1c lmw r27,local_14 (r1)
$U1750 :4 = INT_ADD r1, 28:4
tea = COPY $U1750
r27 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r28 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r29 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r30 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r31 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
00010fcc 80 01 00 34 lwz r0,local_res4 (r1)
$U1750 :4 = INT_ADD r1, 52:4
r0 = LOAD ram($U1750 )
00010fd0 38 21 00 30 addi r1,r1,0x30
r1 = INT_ADD r1, 48:4
00010fd4 7c 08 03 a6 mtspr LR,r0
LR = COPY r0
00010fd8 4e 80 00 20 blr
RETURN LR
```
This whole function is doing 64-bit math (on the GameCube, aka only 32-bit). It's also doing signed math, which it looks like the decompiler treats everything as unsigned right now (see: xor 0x80000000 00000000 to make negative). It also gets confused with some do while loops for some reason
```c void __AI_SRC_INIT(void) { int iVar1; long local_r4_16; long local_r7_220; long local_r8_200; long local_r28_404; int iVar2; OSTime OVar3; OSTime OVar4; OSTime currtime; bool break; local_r4_16 = 0; iVar1 = 0; break = false; local_r28_404 = 0; iVar2 = 0; while (!break) { control = control & 0xffffffdc | 0x21; do { } while (true); OVar4 = OSGetTime(); control = control & 0xfffffffc | 3; do { } while (true); OVar3 = OSGetTime(); iVar1 = (int)((ulonglong)OVar3 >> 0x20); local_r4_16 = (long)OVar3; local_r8_200 = local_r4_16 - (uint)OVar4; local_r7_220 = iVar1 - ((uint)((uint)local_r4_16 < (uint)OVar4) + (int)((ulonglong)OVar4 >> 0x20)) ^ 0x80000000; control = control & 0xfffffffc; if ((uint)local_r7_220 < (uint)((uint)local_r8_200 < bound_32KHz._4_4_ - buffer._4_4_) + (bound_32KHz._0_4_ - ((uint)(bound_32KHz._4_4_ < buffer._4_4_) + buffer._0_4_) ^ 0x80000000)) { break = true; local_r28_404 = min_wait._4_4_; iVar2 = buffer._0_4_; } else { if (((uint)local_r7_220 < (uint)((uint)local_r8_200 < bound_32KHz._4_4_ + buffer._4_4_) + (bound_32KHz._0_4_ + buffer._0_4_ + (uint)CARRY4(bound_32KHz._4_4_,buffer._4_4_) ^ 0x80000000)) || ((uint)((uint)local_r8_200 < bound_48KHz._4_4_ - buffer._4_4_) + (bound_48KHz._0_4_ - ((uint)(bound_48KHz._4_4_ < buffer._4_4_) + buffer._0_4_) ^ 0x80000000) <= (uint)local_r7_220)) { break = false; } else { break = true; local_r28_404 = max_wait._4_4_; iVar2 = max_wait._0_4_; } } } do { OVar4 = OSGetTime(); } while (((uint)((ulonglong)OVar4 >> 0x20) ^ 0x80000000) < (uint)((uint)OVar4 < (uint)(local_r4_16 + local_r28_404)) + (iVar1 + iVar2 + (uint)CARRY4(local_r4_16,local_r28_404) ^ 0x80000000)); return; } ``` from ``` ************************************************************** * FUNCTION ************************************************************** undefined __AI_SRC_INIT () assume r13 = 0xa98 undefined r3:1
long r4:4 local_r4_16 XREF[1]: 00000840 (W)
long r8:4 local_r8_200 XREF[1]: 000008f8 (W)
long r7:4 local_r7_220 XREF[1]: 0000090c (W)
long r28:4 local_r28_404 XREF[1]: 000009c4 (W)
undefined4 Stack[0x4]:4 local_res4 XREF[2]: [more]
undefined4 Stack[-0x18]:4 local_18 XREF[2]: [more]
undefined4 Stack[-0x30]:4 local_30 XREF[1]: 00000838 (W)
OSTime HASH:3f7f054 currtime
bool HASH:79f87e0 break
__AI_SRC_INIT XREF[3]: AISetDSPSampleRate:00000330 (c),
00000830 7c 08 02 a6 mfspr r0,LR
r0 = COPY LR
00000834 90 01 00 04 stw r0,local_res4 (r1)
$U1750 :4 = INT_ADD r1, 4:4
STORE ram($U1750 ), r0
00000838 94 21 ff d0 stwu r1,local_30 (r1)
$U1790 :4 = INT_ADD r1, 0xffffffd0 :4
STORE ram($U1790 ), r1
r1 = COPY $U1790
0000083c bf 41 00 18 stmw r26,local_18 (r1)
$U1750 :4 = INT_ADD r1, 24:4
tea = COPY $U1750
STORE ram(tea), r26
tea = INT_ADD tea, 4:4
STORE ram(tea), r27
tea = INT_ADD tea, 4:4
STORE ram(tea), r28
tea = INT_ADD tea, 4:4
STORE ram(tea), r29
tea = INT_ADD tea, 4:4
STORE ram(tea), r30
tea = INT_ADD tea, 4:4
STORE ram(tea), r31
tea = INT_ADD tea, 4:4
00000840 38 80 00 00 li local_r4_16 ,0x0
r4 = COPY 0:4
00000844 38 60 00 00 li r3,0x0
r3 = COPY 0:4
00000848 38 00 00 00 li r0,0x0
r0 = COPY 0:4
0000084c 3b 80 00 00 li r28,0x0
r28 = COPY 0:4
00000850 3b a0 00 00 li r29,0x0
r29 = COPY 0:4
00000854 48 00 00 04 b LAB_00000858
BRANCH *[ram]0x858:4
LAB_00000858 XREF[1]: 00000854 (j)
00000858 3f e0 cc 00 lis r31,-0x3400
r31 = INT_LEFT 0xffffcc00 :4, 16:4
0000085c 48 00 00 04 b LAB_00000860
BRANCH *[ram]0x860:4
LAB_00000860 XREF[1]: 0000085c (j)
00000860 48 00 01 64 b LAB_000009c4
BRANCH *[ram]0x9c4:4
LAB_00000864 XREF[1]: 000009c8 (j)
00000864 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
00000868 3b df 6c 00 addi r30,r31,0x6c00
r30 = INT_ADD r31, 0x6c00 :4
0000086c 3b de 00 08 addi r30,r30,0x8
r30 = INT_ADD r30, 8:4
00000870 54 00 06 f2 rlwinm r0,r0,0x0,0x1b,0x19
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xffffffdf :4
00000874 60 00 00 20 ori r0,r0,0x20
r0 = INT_OR r0, 32:4
00000878 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
0000087c 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
00000880 54 00 07 fa rlwinm r0,r0,0x0,0x1f,0x1d
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xfffffffd :4
00000884 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
00000888 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
0000088c 54 00 00 3c rlwinm r0,r0,0x0,0x0,0x1e
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xfffffffe :4
00000890 60 00 00 01 ori r0,r0,0x1
r0 = INT_OR r0, 1:4
00000894 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
00000898 80 7e 00 00 lwz r3,0x0(r30)=>samples
$U1750 :4 = INT_ADD r30, 0:4
r3 = LOAD ram($U1750 )
0000089c 48 00 00 04 b LAB_000008a0
BRANCH *[ram]0x8a0:4
LAB_000008a0 XREF[1]: 0000089c (j)
000008a0 48 00 00 04 b LAB_000008a4
BRANCH *[ram]0x8a4:4
LAB_000008a4 XREF[2]: 000008a0 (j), [more]
000008a4 80 1e 00 00 lwz r0,0x0(r30)=>samples
$U1750 :4 = INT_ADD r30, 0:4
r0 = LOAD ram($U1750 )
000008a8 7c 03 00 40 cmplw r3,r0
$U2900 :4 = COPY r3
$U2910 :4 = COPY r0
$U2920 :1 = INT_LESS $U2900 , $U2910
$U2930 :1 = INT_LEFT $U2920 , 3:4
$U2940 :1 = INT_LESS $U2910 , $U2900
$U2950 :1 = INT_LEFT $U2940 , 2:4
$U2960 :1 = INT_OR $U2930 , $U2950
$U2970 :1 = INT_EQUAL $U2900 , $U2910
$U2980 :1 = INT_LEFT $U2970 , 1:4
$U2990 :1 = INT_OR $U2960 , $U2980
$U29a0 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2990 , $U29a0
000008ac 41 82 ff f8 beq LAB_000008a4
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x8a4:4, $U1440
000008b0 48 00 07 6d bl OSGetTime OSTime OSGetTime(void)
r2Save = COPY r2
LR = COPY 0x8b4:4
CALL *[ram]0x101c :4
000008b4 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
000008b8 7c 9a 23 78 or r26,local_r4_16 ,local_r4_16
r26 = INT_OR r4, r4
000008bc 7c 7b 1b 78 or r27,r3,r3
r27 = INT_OR r3, r3
000008c0 54 00 07 fa rlwinm r0,r0,0x0,0x1f,0x1d
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xfffffffd :4
000008c4 60 00 00 02 ori r0,r0,0x2
r0 = INT_OR r0, 2:4
000008c8 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
000008cc 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
000008d0 54 00 00 3c rlwinm r0,r0,0x0,0x0,0x1e
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xfffffffe :4
000008d4 60 00 00 01 ori r0,r0,0x1
r0 = INT_OR r0, 1:4
000008d8 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
000008dc 80 7e 00 00 lwz r3,0x0(r30)=>samples
$U1750 :4 = INT_ADD r30, 0:4
r3 = LOAD ram($U1750 )
000008e0 48 00 00 04 b LAB_000008e4
BRANCH *[ram]0x8e4:4
LAB_000008e4 XREF[1]: 000008e0 (j)
000008e4 48 00 00 04 b LAB_000008e8
BRANCH *[ram]0x8e8:4
LAB_000008e8 XREF[2]: 000008e4 (j), [more]
000008e8 80 1e 00 00 lwz r0,0x0(r30)=>samples
$U1750 :4 = INT_ADD r30, 0:4
r0 = LOAD ram($U1750 )
000008ec 7c 03 00 40 cmplw r3,r0
$U2900 :4 = COPY r3
$U2910 :4 = COPY r0
$U2920 :1 = INT_LESS $U2900 , $U2910
$U2930 :1 = INT_LEFT $U2920 , 3:4
$U2940 :1 = INT_LESS $U2910 , $U2900
$U2950 :1 = INT_LEFT $U2940 , 2:4
$U2960 :1 = INT_OR $U2930 , $U2950
$U2970 :1 = INT_EQUAL $U2900 , $U2910
$U2980 :1 = INT_LEFT $U2970 , 1:4
$U2990 :1 = INT_OR $U2960 , $U2980
$U29a0 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2990 , $U29a0
000008f0 41 82 ff f8 beq LAB_000008e8
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x8e8:4, $U1440
000008f4 48 00 07 29 bl OSGetTime OSTime OSGetTime(void)
r2Save = COPY r2
LR = COPY 0x8f8:4
CALL *[ram]0x101c :4
000008f8 7d 1a 20 10 subfc local_r8_200 ,r26,local_r4_16
xer_ca = INT_LESSEQUAL r26, r4
r8 = INT_SUB r4, r26
000008fc 81 8d 00 24 lwz r12,0x24(r13)=>bound_32KHz+4 = null
$U1750 :4 = INT_ADD r13, 36:4
r12 = LOAD ram($U1750 )
00000900 80 bf 6c 00 lwz r5,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r5 = LOAD ram($U1750 )
00000904 7c fb 19 10 subfe r7,r27,r3
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r27
xer_ca = INT_LESSEQUAL $U70a0 , r3
r7 = INT_SUB r3, $U70a0
00000908 81 4d 00 44 lwz r10,0x44(r13)=>buffer+4 = null
$U1750 :4 = INT_ADD r13, 0x44:4
r10 = LOAD ram($U1750 )
0000090c 6c e7 80 00 xoris local_r7_220 ,local_r7_220 ,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r7 = INT_XOR r7, $U76a0
00000910 54 a5 07 fa rlwinm r5,r5,0x0,0x1f,0x1d
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r5, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r5, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r5 = INT_AND $U67c0 , 0xfffffffd :4
00000914 81 6d 00 20 lwz r11,0x20(r13)=>bound_32KHz = ??
$U1750 :4 = INT_ADD r13, 32:4
r11 = LOAD ram($U1750 )
00000918 7c ca 60 10 subfc r6,r10,r12
xer_ca = INT_LESSEQUAL r10, r12
r6 = INT_SUB r12, r10
0000091c 81 2d 00 40 lwz r9,0x40(r13)=>buffer = ??
$U1750 :4 = INT_ADD r13, 64:4
r9 = LOAD ram($U1750 )
00000920 90 bf 6c 00 stw r5,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r5
00000924 7c 09 59 10 subfe r0,r9,r11
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r9
xer_ca = INT_LESSEQUAL $U70a0 , r11
r0 = INT_SUB r11, $U70a0
00000928 6c 05 80 00 xoris r5,r0,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r5 = INT_XOR r0, $U76a0
0000092c 7c 06 40 10 subfc r0,r6,local_r8_200
xer_ca = INT_LESSEQUAL r6, r8
r0 = INT_SUB r8, r6
00000930 80 1f 6c 00 lwz r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
r0 = LOAD ram($U1750 )
00000934 7c a5 39 10 subfe r5,r5,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r5
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
00000938 7c a7 39 10 subfe r5,local_r7_220 ,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r7
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
0000093c 7c a5 00 d0 neg r5,r5
r5 = INT_2COMP r5
00000940 54 00 00 3c rlwinm r0,r0,0x0,0x0,0x1e
$U6770 :1 = COPY 0:1
$U6780 :4 = INT_LEFT r0, $U6770
$U6790 :1 = INT_SUB 32:1, $U6770
$U67a0 :4 = INT_RIGHT r0, $U6790
$U67c0 :4 = INT_OR $U6780 , $U67a0
r0 = INT_AND $U67c0 , 0xfffffffe :4
00000944 2c 05 00 00 cmpwi r5,0x0
$U2780 :4 = COPY r5
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00000948 90 1f 6c 00 stw r0,offset control (r31)
$U1750 :4 = INT_ADD r31, 0x6c00 :4
STORE ram($U1750 ), r0
0000094c 41 82 00 14 beq LAB_00000960
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x960:4, $U1440
00000950 83 ad 00 40 lwz r29,0x40(r13)=>buffer = ??
$U1750 :4 = INT_ADD r13, 64:4
r29 = LOAD ram($U1750 )
00000954 38 00 00 01 li r0,0x1
r0 = COPY 1:4
00000958 83 8d 00 34 lwz r28,0x34(r13)=>min_wait+4 = null
$U1750 :4 = INT_ADD r13, 52:4
r28 = LOAD ram($U1750 )
0000095c 48 00 00 68 b LAB_000009c4
BRANCH *[ram]0x9c4:4
LAB_00000960 XREF[1]: 0000094c (j)
00000960 7c cc 50 14 addc r6,r12,r10
xer_ca = INT_CARRY r12, r10
r6 = INT_ADD r12, r10
00000964 7c 0b 49 14 adde r0,r11,r9
$U1d80 :4 = INT_ZEXT xer_ca
xer_ca = INT_CARRY r9, $U1d80
$U1db0 :4 = INT_ADD r9, $U1d80
$U1dc0 :1 = INT_CARRY r11, $U1db0
xer_ca = BOOL_OR xer_ca , $U1dc0
r0 = INT_ADD r11, $U1db0
00000968 6c 05 80 00 xoris r5,r0,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r5 = INT_XOR r0, $U76a0
0000096c 7c 06 40 10 subfc r0,r6,local_r8_200
xer_ca = INT_LESSEQUAL r6, r8
r0 = INT_SUB r8, r6
00000970 7c a5 39 10 subfe r5,r5,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r5
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
00000974 7c a7 39 10 subfe r5,local_r7_220 ,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r7
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
00000978 7c a5 00 d0 neg r5,r5
r5 = INT_2COMP r5
0000097c 2c 05 00 00 cmpwi r5,0x0
$U2780 :4 = COPY r5
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
00000980 40 82 00 40 bne LAB_000009c0
$U1480 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1480 :1 = INT_AND $U120, 1:1
$U1480 :1 = BOOL_NEGATE $U1480
CBRANCH *[ram]0x9c0:4, $U1480
00000984 80 ad 00 2c lwz r5,0x2c(r13)=>bound_48KHz+4 = null
$U1750 :4 = INT_ADD r13, 44:4
r5 = LOAD ram($U1750 )
00000988 80 0d 00 28 lwz r0,0x28(r13)=>bound_48KHz = ??
$U1750 :4 = INT_ADD r13, 40:4
r0 = LOAD ram($U1750 )
0000098c 7c ca 28 10 subfc r6,r10,r5
xer_ca = INT_LESSEQUAL r10, r5
r6 = INT_SUB r5, r10
00000990 7c 09 01 10 subfe r0,r9,r0
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r9
xer_ca = INT_LESSEQUAL $U70a0 , r0
r0 = INT_SUB r0, $U70a0
00000994 6c 05 80 00 xoris r5,r0,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r5 = INT_XOR r0, $U76a0
00000998 7c 06 40 10 subfc r0,r6,local_r8_200
xer_ca = INT_LESSEQUAL r6, r8
r0 = INT_SUB r8, r6
0000099c 7c a5 39 10 subfe r5,r5,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r5
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
000009a0 7c a7 39 10 subfe r5,local_r7_220 ,local_r7_220
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r7
xer_ca = INT_LESSEQUAL $U70a0 , r7
r5 = INT_SUB r7, $U70a0
000009a4 7c a5 00 d0 neg r5,r5
r5 = INT_2COMP r5
000009a8 2c 05 00 00 cmpwi r5,0x0
$U2780 :4 = COPY r5
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
000009ac 41 82 00 14 beq LAB_000009c0
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x9c0:4, $U1440
000009b0 83 ad 00 38 lwz r29,0x38(r13)=>max_wait = ??
$U1750 :4 = INT_ADD r13, 56:4
r29 = LOAD ram($U1750 )
000009b4 38 00 00 01 li r0,0x1
r0 = COPY 1:4
000009b8 83 8d 00 3c lwz r28,0x3c(r13)=>max_wait+4 = null
$U1750 :4 = INT_ADD r13, 60:4
r28 = LOAD ram($U1750 )
000009bc 48 00 00 08 b LAB_000009c4
BRANCH *[ram]0x9c4:4
LAB_000009c0 XREF[2]: 00000980 (j), [more]
000009c0 38 00 00 00 li r0,0x0
r0 = COPY 0:4
LAB_000009c4 XREF[3]: 00000860 (j), [more]
000009c4 28 00 00 00 cmplwi r0,0x0
$U2a80 :4 = COPY r0
$U2a90 :4 = COPY 0:4
$U2aa0 :1 = INT_LESS $U2a80 , $U2a90
$U2ab0 :1 = INT_LEFT $U2aa0 , 3:4
$U2ac0 :1 = INT_LESS $U2a90 , $U2a80
$U2ad0 :1 = INT_LEFT $U2ac0 , 2:4
$U2ae0 :1 = INT_OR $U2ab0 , $U2ad0
$U2af0 :1 = INT_EQUAL $U2a80 , $U2a90
$U2b00 :1 = INT_LEFT $U2af0 , 1:4
$U2b10 :1 = INT_OR $U2ae0 , $U2b00
$U2b20 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2b10 , $U2b20
000009c8 41 82 fe 9c beq LAB_00000864
$U1440 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1440 :1 = INT_AND $U120, 1:1
CBRANCH *[ram]0x864:4, $U1440
000009cc 7f 64 e0 14 addc r27,local_r4_16 ,local_r28_404
xer_ca = INT_CARRY r4, r28
r27 = INT_ADD r4, r28
000009d0 7f 43 e9 14 adde r26,r3,r29
$U1d80 :4 = INT_ZEXT xer_ca
xer_ca = INT_CARRY r29, $U1d80
$U1db0 :4 = INT_ADD r29, $U1d80
$U1dc0 :1 = INT_CARRY r3, $U1db0
xer_ca = BOOL_OR xer_ca , $U1dc0
r26 = INT_ADD r3, $U1db0
000009d4 48 00 00 04 b LAB_000009d8
BRANCH *[ram]0x9d8:4
LAB_000009d8 XREF[1]: 000009d4 (j)
000009d8 48 00 00 04 b LAB_000009dc
BRANCH *[ram]0x9dc:4
LAB_000009dc XREF[2]: 000009d8 (j), [more]
000009dc 48 00 06 41 bl OSGetTime OSTime OSGetTime(void)
r2Save = COPY r2
LR = COPY 0x9e0:4
CALL *[ram]0x101c :4
000009e0 6c 65 80 00 xoris r5,r3,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r5 = INT_XOR r3, $U76a0
000009e4 6f 43 80 00 xoris r3,r26,0x8000
$U76a0 :4 = INT_LEFT 0x8000 :4, 16:4
r3 = INT_XOR r26, $U76a0
000009e8 7c 1b 20 10 subfc r0,r27,local_r4_16
xer_ca = INT_LESSEQUAL r27, r4
r0 = INT_SUB r4, r27
000009ec 7c 63 29 10 subfe r3,r3,r5
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r3
xer_ca = INT_LESSEQUAL $U70a0 , r5
r3 = INT_SUB r5, $U70a0
000009f0 7c 65 29 10 subfe r3,r5,r5
$U7070 :1 = BOOL_NEGATE xer_ca
$U7080 :4 = INT_ZEXT $U7070
$U70a0 :4 = INT_ADD $U7080 , r5
xer_ca = INT_LESSEQUAL $U70a0 , r5
r3 = INT_SUB r5, $U70a0
000009f4 7c 63 00 d0 neg r3,r3
r3 = INT_2COMP r3
000009f8 2c 03 00 00 cmpwi r3,0x0
$U2780 :4 = COPY r3
$U2790 :4 = COPY 0:4
$U27a0 :1 = INT_SLESS $U2780 , $U2790
$U27b0 :1 = INT_LEFT $U27a0 , 3:4
$U27c0 :1 = INT_SLESS $U2790 , $U2780
$U27d0 :1 = INT_LEFT $U27c0 , 2:4
$U27e0 :1 = INT_OR $U27b0 , $U27d0
$U27f0 :1 = INT_EQUAL $U2780 , $U2790
$U2800 :1 = INT_LEFT $U27f0 , 1:4
$U2810 :1 = INT_OR $U27e0 , $U2800
$U2820 :1 = INT_AND xer_so , 1:1
cr0 = INT_OR $U2810 , $U2820
000009fc 40 82 ff e0 bne LAB_000009dc
$U1480 :1 = COPY 0:1
$U100:4 = INT_SUB 3:4, 2:4
$U120:1 = INT_RIGHT cr0, $U100
$U1480 :1 = INT_AND $U120, 1:1
$U1480 :1 = BOOL_NEGATE $U1480
CBRANCH *[ram]0x9dc:4, $U1480
00000a00 bb 41 00 18 lmw r26,local_18 (r1)
$U1750 :4 = INT_ADD r1, 24:4
tea = COPY $U1750
r26 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r27 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r28 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r29 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r30 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
r31 = LOAD ram(tea)
tea = INT_ADD tea, 4:4
00000a04 80 01 00 34 lwz r0,local_res4 (r1)
$U1750 :4 = INT_ADD r1, 52:4
r0 = LOAD ram($U1750 )
00000a08 38 21 00 30 addi r1,r1,0x30
r1 = INT_ADD r1, 48:4
00000a0c 7c 08 03 a6 mtspr LR,r0
LR = COPY r0
00000a10 4e 80 00 20 blr
RETURN LR
```