Proper binary logic gate functionality

[micmac253]

Is your feature request related to a problem? Please describe.

Ive ran into a problem. when trying to make complex binary logic you need a few simple things, gates, latches, and flip flops. Yes there is a boolean latch but that is an SR latch, you also need a fire while true for every input and that is bulky and not needed for what I am doing. Now in order to create more advanced latches and flip flops you have to make an SR latch first, but to make an SR latch you have to take two NOR gates and wire the outputs of each into the inputs of the other and if you try this in game it will refuse to let you connect the other sides output to the input. Here is an image of a simple SR flip-flop and a gated D-latch, both of these are not possible to make in their current form and the gated D-latch Im fairly certain is not even possible to make.

Relevant issues

none

Describe the solution you'd like

two methods of addressing this issue are to either make it so the output of gates can go into the input of another (see above pictures), or and more dedicated binary nodes, ie. every type of latch and flip flop. if the latter option is chosen to be more feasible then I would ask that the inputs and outputs are ONLY boolean and NOT pulse, dealing with pulses in a full binary circuit is a headache.

Describe alternatives you've considered

above text shows 2 viable methods of addressing this issue.

Additional context

No response

[RobertBaruch]

Just a comment. In design of FPGA and ASIC circuitry, you never design in gates like the above due to metastability issues. You only use the chip's native flip-flops. Designers draw a distinction between combinatorial logic and synchronous (i.e. clocked) logic. Impulses are great for clocked logic, while values are great for combinatorial logic.

The gate you have above, while it may be the implementation of a flip-flop, is neither combinatoric nor synchronous.

I'm sure you know this :>

Neos prevents value cycles because they would potentially lead to infinite evaluation and in any case would lead to undefined behavior. I also note that Neos prevents evaluation depth greater than 512 steps.

In addition, designers have to build in special circuitry when crossing clock domains (i.e. signals that are triggered on different clocks), so that gets even hairier.

As for the solution, perhaps a workaround is to use the Fire On True and Fire On False nodes. For example, here's my implementation of an SR flip-flop:

It's also implicitly clocked, because the Fire nodes will only fire on update cycles.

Yes, it's nicer to have a single node that does this. But until we get something like function blocks, that's probably the best we can do.

[micmac253]

Just a comment. In design of FPGA and ASIC circuitry, you never design in gates like the above due to metastability issues. You only use the chip's native flip-flops. Designers draw a distinction between combinatorial logic and synchronous (i.e. clocked) logic. Impulses are great for clocked logic, while values are great for combinatorial logic.

The gate you have above, while it may be the implementation of a flip-flop, is neither combinatoric nor synchronous.

I'm sure you know this :>

Neos prevents value cycles because they would potentially lead to infinite evaluation and in any case would lead to undefined behavior. I also note that Neos prevents evaluation depth greater than 512 steps.

In addition, designers have to build in special circuitry when crossing clock domains (i.e. signals that are triggered on different clocks), so that gets even hairier.

As for the solution, perhaps a workaround is to use the Fire On True and Fire On False nodes. For example, here's my implementation of an SR flip-flop:

It's also implicitly clocked, because the Fire nodes will only fire on update cycles.

Yes, it's nicer to have a single node that does this. But until we get something like function blocks, that's probably the best we can do.

what I am specifically trying to create is a memory register using data flip-flops. its just a small part of my bigger plan to create a computer. here is a picture of the exact logic I was trying to make, it almost worked but not quite. the inputs at the bottom starting from the left are Store, Data, and Clock.

[RobertBaruch]

One problem is that you actually have three clocks (I'm assuming the "st" signal is a clock input). One for the right latch, one for the left, and one that's inverted. Best practice is to make everything synchronous, so all on one clock edge. Well-behaved synchronous circuits can be described as large amounts of combinatorial logic, with clocked state. Think Mealy/Moore state machines. Designing circuits where elements are clocked based on unclocked signals is just asking for trouble :>

[Irick]

I've run into a similar issue trying to implement a model And-Or latch for an attempt at some lesson aids for a basic computer science course. Specifically, LogiX doesn't like me connecting the output of the AND into the OR. I was able to get the circuit to work using a Write to a Boolean Register, but it really complicates the circuit visually and conceptually.