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Neotron-Compute / Neotron-Pico-BIOS

BIOS for the Neotron Pico
GNU General Public License v3.0
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Fix screen alignment #70

Closed thejpster closed 11 months ago

thejpster commented 12 months ago

The screen is offset by a couple of rows. You can tell because a couple of lines of blue pixels (I think from the bottom of the previous frame) appear at the top of the frame.

This is partly caused by the DMA completion triggering the next DMA. This means the top line starts to transfer into the pixel FIFO before the vertical blanking interval even starts.

Instead we should trigger a CPU interrupt from the timing SM (as all as the IRQ for the pixel SM, which triggers playout of the pixels). This CPU interrupt should be used to trigger rendering of the next line as well as DMA loading of the current line.

thejpster commented 12 months ago

If we trigger at the start of the front porch, we have 960 CPU clock cycles (roughly) before the pixel SM is going to start draining its FIFO. That seems plenty to set up a DMA transfer, and enter the main thread on Core 1 to do a render.