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NetFPGA 1G CML Live development repository
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Issue during make cml_cores -- missing trimac.xcf file. #14

Closed stefan-niedermayr closed 4 years ago

stefan-niedermayr commented 4 years ago

Hello everybody,

I'm rather new to the NetFPGA system, so bare with me if I made some mistakes. Currently I'm stuck at getting reference projects running on the NetFPGA 1G CML board. I can program the already existing bistreams without any problems, but seem to have troubles generating projects.

When I follow the getting started guide step by step, it failes at the make cml_cores step. Unfortunately it seems that the trimac.xcf file is missing in the repository? Does anybody have an idea where i made the wrong turn or tips on how to fix this?

If you need further information, please let me know.

Thanks in advance!

Output from make make cml_cores:

Delivering associated files for 'trimac'... Delivering EJava files for 'trimac'... Generating implementation netlist for 'trimac'... INFO:sim - Pre-processing HDL files for 'trimac'... WARNING:sim - BlackBox generator run option '-iobuf' found multiple times. Only the first occurence is considered. Running synthesis for 'trimac' ERROR:sim - Cannot open file '/home/stefan-e495/Git/NetFPGA-1G-CML-live/lib/hw/contrib/pcores/nf1_cml_inte rface_v1_00_a/trimac_work/tmp/_cg/_dbg/trimac.xcf'. Please make sure that the file exists and that you have read permission for it. ERROR:sim - Failed executing Tcl generator. ERROR:sim - Failed to generate 'trimac'. Failed executing Tcl generator.

System:

Pop_OS 19.10 Xilinx ISE 14.6 (30-day evaluation license)

salvatorg commented 4 years ago

Might it be license related? Check the Xilinx licenses which are required.

stefan-niedermayr commented 4 years ago

Hi salvatorg,

thanks for the reply. I think I can elimiate the license, since it is the 30-day-trial version which includes full access to all features and all Xilinx provided IPs. Creating projects for the Kintex7 325 works just fine, which is normally prohibited in the WebPack Edition. What I found out is, that the .xcf file is physically not at the required location. So far I'm not sure, if it is supposed to be created during the make process, or be there anyway.

BR, Stefan

salvatorg commented 4 years ago

To be sure, can you check from the Xilinx License Configuration Manager if it shows any license?

stefan-niedermayr commented 4 years ago

Sure - license manager shows the following as valid licenses until 02-may-2020:

Analyzer ChipScopePro_SIOTK ChipScopePro HLS HLS ISE ISE_System_Edition ISIM Implementation PartialReconfiguration PlanAhead SDK Simulation Synthesis SysGen SysGen Vivado_System_Edition XPS

All are nodelocked licenses.

salvatorg commented 4 years ago

What about any IP core (i.e. TEMAC )? That worries me a bit. You can try to create the evaluation license for the specific IP core from here

There is another solution that might work without this license. Try to run make cores instead of make cml_cores

stefan-niedermayr commented 4 years ago

Thank you salvatorg. Using make cores instead of make cml_cores brought me one step further, which now revealed maybe the main underlying issue. As it seems, allthough I've created and installed the evaluation license for Vivado/ISE and the Trimac IP, it does not recognize it during the make process. I have Vivado (2019.2) aswell as ISE (14.6) installed, both in separate directories - maybe this is causing me troubles? What is also strange, is that every license in the new license manager from the Vivado-Install is accepted and valid, where as in the license manager of ISE it seems that it can not retrieve the NIC required to validate "Host Id Matches". Therefore in the later, this may cause the issues making the reference projects.

Projects created in Vivado work just fine on the XC7K325T.

You don't seem to have come across such a problem?

Include the "new" license issue console output.

Thanks a lot for taking time and helping me out :)

Best Regards!

`**** Creating system netlist for hardware specification..

platgen -p xc7k325tffg676-1 -lang verilog -intstyle default -lp /home/stefan-e495/Git/NetFPGA-1G-CML-live/projects/loopback_test_nf1_cml/lib/ -msg __xps/ise/xmsgprops.lst -parallel yes system.mhs

Release 14.6 - platgen Xilinx EDK 14.6 Build EDK_P.68d (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Command Line: platgen -p xc7k325tffg676-1 -lang verilog -intstyle default -lp /home/stefan-e495/Git/NetFPGA-1G-CML-live/projects/loopback_test_nf1_cml/lib/ -msg __xps/ise/xmsgprops.lst -parallel yes system.mhs

ERROR:EDK - INFO:Security:67 - XILINXD_LICENSE_FILE is set to '/opt/Xilinx/Vivado/2019.2/data/ip/core_licenses' in /home/stefan-e495/.flexlmrc. INFO:Security:71 - If a license for part 'xc7k325t' is available, it will be possible to use 'XPS_TDP' instead of 'XPS'. INFO:Security:7 - A feature for XPS was found but is for the wrong hostid. INFO:Security:68 - For more information or for assistance in obtaining a license, please run the Xilinx License Configuration Manager (xlcm or "Manage Xilinx Licenses".) INFO:Security:68a - user is stefan-e495, on host unknown. WARNING:Security:9b - No 'XPS' feature version 2013.06 was available for part 'xc7k325t'. ERROR:Security:12 - No 'xc7k325t' feature version 2013.06 was available (-15), so 'XPS_TDP' may not be used.

Invalid host. The hostid of this system does not match the hostid specified in the license file. Feature: XPS Hostid: 482ae3479cc6 License path: /opt/Xilinx/Vivado/2019.2/data/ip/core_licenses/Xilinx.lic:/opt/Xilinx/Vivado /2019.2/data/ip/core_licenses/XilinxFree.lic:/home/stefan-e495/.Xilinx/Xilinx .lic:/home/stefan-e495/.Xilinx/Xilinx_Trimac.lic:/opt/Xilinx-ISE/14.6/ISE_DS/ ISE/data/.lic:/opt/Xilinx-ISE/14.6/ISE_DS/ISE/coregen/core_licenses/Xilinx.l ic:/opt/Xilinx-ISE/14.6/ISE_DS/EDK/data/core_licenses/Xilinx.lic:@localhost: FLEXnet Licensing error:-9,57 For further information, refer to the FLEXnet Licensing documentation, available at "www.flexerasoftware.com".Cannot connect to license server system. The license server manager (lmgrd) has not been started yet, the wrong port@host or license file is being used, or the port or hostname in the license file has been changed. Feature: xc7k325t Server name: localhost License path: /opt/Xilinx/Vivado/2019.2/data/ip/core_licenses/Xilinx.lic:/opt/Xilinx/Vivado /2019.2/data/ip/core_licenses/XilinxFree.lic:/home/stefan-e495/.Xilinx/Xilinx .lic:/home/stefan-e495/.Xilinx/Xilinx_Trimac.lic:/opt/Xilinx-ISE/14.6/ISE_DS/ ISE/data/.lic:/opt/Xilinx-ISE/14.6/ISE_DS/ISE/coregen/core_licenses/Xilinx.l ic:/opt/Xilinx-ISE/14.6/ISE_DS/EDK/data/core_licenses/Xilinx.lic:@localhost: FLEXnet Licensing error:-15,570. System Error: 115 "Operation now in progress" For further information, refer to the FLEXnet Licensing documentation, available at "www.flexerasoftware.com". ERROR:EDK - platgen failed with errors! make[2]: [system.make:128: implementation/system.bmm] Error 2 make[2]: Leaving directory '/home/stefan-e495/Git/NetFPGA-1G-CML-live/projects/loopback_test_nf1_cml/hw' make[1]: [Makefile:44: bits] Error 2 make[1]: Leaving directory '/home/stefan-e495/Git/NetFPGA-1G-CML-live/projects/loopback_test_nf1_cml/hw' `

salvatorg commented 4 years ago

It seems that your environment variables for ISE are not set properly and they are currently set to Vivado. The XILINXD_LICENSE_FILE environment variable points to the location where this license is located Can you echo this variable XILINXD_LICENSE_FILE ? if nothing appears then set it to the license location.

stefan-niedermayr commented 4 years ago

Hi salvatorg, sorry for the late reply, had to put this issue on hold for a few days to figure out something else. One issue I could eliminate so far, is that the Xilinx ISE License Manager now recognizes my NIC and therefore all licenses are active and accepted.

The issue was mentioned in AR# 60510. It seems that Xilinx ISE License Manager can not deal with the now common new ethernet interface naming conventions and requires eth0 and similar. This could be fixed by renaming the ethernet interface.

ifconfig <enx-interfacename> down  

ip link set <enx-interfacename> name eth0  

ifconfig eth0 up

It seems that Xilinx license manager still has issues with "Host Id Matches" allthough it is displayed correctly in the NIC ID field. The AR# 56505 make it seem that this might just be a display issue and should not affect the usage.

The variable XILINXD_LICENSE_FILE was not set. Setting it export XILINXD_LICENSE_FILE=<absolute-path-to-lic-file> did not change anything.

Unfortunately I'm still stuck were I started. Both make cores and make cml_cores fail similarly.

`Release 14.6 - Xilinx CORE Generator P.68d (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. All runtime messages will be recorded in /home/stefan-e495/Git/NetFPGA-1G-CML-live/lib/hw/contrib/pcores/nf1_cml_interfac e_v1_00_a/trimac_work/coregen.log INFO:encore:314 - Created non-GUI application for batch mode execution. Saved CGP file for project 'coregen'. INFO:sim:172 - Generating IP... Resolving generics for 'trimac'... Applying external generics to 'trimac'... Delivering associated files for 'trimac'... Delivering EJava files for 'trimac'... Generating implementation netlist for 'trimac'... INFO:sim - Pre-processing HDL files for 'trimac'... WARNING:sim - BlackBox generator run option '-iobuf' found multiple times. Only the first occurence is considered. Running synthesis for 'trimac' ERROR:sim - Cannot open file '/home/stefan-e495/Git/NetFPGA-1G-CML-live/lib/hw/contrib/pcores/nf1_cml_inte rface_v1_00_a/trimac_work/tmp/_cg/_dbg/trimac.xcf'. Please make sure that the file exists and that you have read permission for it. ERROR:sim - Failed executing Tcl generator. ERROR:sim - Failed to generate 'trimac'. Failed executing Tcl generator.

ERROR:sim:877 - Error found during execution of IP 'Tri Mode Ethernet MAC v5.5' make[1]: *** [Makefile:60: netlist/trimac.ngc] Error 1 `

Thank you for your help! Best regards!

blacksandland commented 4 years ago

I will echo the same exact issue on my very similar setup (except OS is Fedora 30 --> 14 and 20 would not play nice with Fedora Eclipse for me).

There is a recent thread on the Xilinx forum where the Xilinx folks suggest the following:

"To work around this issue:

Select Project Options -> Generation. Change the Design Entry option from "VHDL" to "Verilog". Generate the IP core."

However - like others on that thread - I can't find where to change "Project options -> Generation entries".

Also I don't get the error described by the Xilinx folks where "VHDL is not a supported wrapper" - for that solution to be applicable...

Thanks for any continued help! Stay safe!

blacksandland commented 4 years ago

Actually I found the Project Options - option. Its under the "Core Gen" tool - and you have to look for the little book icon thing on the right of the toolbar, it will tool assist as "Project Options". However this is predicated on finding the correct "Core" which appears to be generated under the trimac_work folder as "coregen.cgp".

Reviewing the project options once the trimac_work/coregen.cgp file is loaded - the part family is listed as virtex 7 and NOT kintex-7 (along with the incorrect device descriptor, and other incorrect parameters...).

The Xilinx forum post is correct in that the design entry is set to VHDL for the aforementioned 'core" --> however I don't see the "The CORE Generator tool should be issuing a warning indicating that VHDL is not supported as a wrapper file for the selected IP and that the Verilog wrapper will be generated." warning...

Additionally if I make the changes suggested and save the changes - the regenerate core option is still greyed out. So this sounds like it needs to happen upstream somewhere from what ever trimac_work is built from.

The "trimac.xco" file appears to have the correct Xilinx core gen parameters set for the 1G-CML pcie hw - but this doesn't make sense. The Core Gen (as I understand it) should be loading "Tri Mode Ethernet MAC (v5.5)" IP and relaying the trimac.xco customization's and generating the coregen.cgp appropriately - but this does not appear to be happening. When I go to load the "Tri Mode Ethernet MAC (v5.5)" myself I get a license error where I can't apply changes to hardware - only simulations... This would lead to the "license" work around "stefan-niedermayr" applied - but that apparently doesn't work either in the long run...

stefan-niedermayr commented 4 years ago

Hi blacksandland,

sorry to hear that you've also running into issues here. Might I ask a dumb question, since I'm really struggling here with NetFPGA projects and ISE in general - how do you even open those projects in ISE? I can't seem to find any project files (*.xise ?) that would allow for that. Unfortunately, currently I only know my way around in Vivado.

Have you tried out renaming your ethernet interface to something like eth0 and try it again?

Best regards!

blacksandland commented 4 years ago

I am a neophyte to the NeFPGA and to an extent the Xilinx landscape as well but trying to dive in for a research project... Just FYI

I couldn't find a project file either - but there are several *.cpg files to be found that the Core Generator tool will open (without a project file) - but when running the initial install of the make cml_cores - it appears the coregen.cpg file is created during the make process (I haven't reviewed the make file closely yet). You can't find it until you run the make cml_cores command...

** to be clear when I mention the "coregen.cpg" file, I am referring to the file that is created under the "nf1_cml_interface_v1_00_a/trimac_work/" (project) directory. NOT one of the coregen.cpg files in other folders.

If you run the make clean and make hwtestlibclean commands it removes the trimac_work directory and files (including the coregen.cpg file). So the Xilinx suggestion is curious because its like a chicken and egg solution - how to make one happen first --> that's why I am fishing upstream somewhere to investigate the trimac.xco file - where it is generated from etc... It could be a rabbit hole - but who knows...

I think there is a definite disconnect in my licensing based on the Core Generator popup dialog - but I don't think (like you said) that is the total solution to the trimac.xcf missing file error.

(to regerate the coregen.cpg file after the xilinx suggestion noted above - the license has to be in place --> its clear now why the 'regenerate core option' is greyed out - because of the license issue...)

I haven't done the license / Ethernet renaming fix you suggested yet - that is on today's agenda along with trying a couple different Linux kernel versions. Keep plugging - and maybe between the three of us (Salvator has been great!) we can get this figured out...

Cheers!

stefan-niedermayr commented 4 years ago

Ok, now I've made some progress today understanding the whole makefile setup and coregen a little better. You are right that it seems to fail at the corgen batch process step.

What I've tried so far working in the /lib/hw/contrib/pcores/nf1_cml_interface_v1_00_a dir:

So, I guess we have to dig deeper. It seems something going on with ISE/Coregen. Not sure if it is related to NetFPGA project, or the system we are running this on.

Best regards.

salvatorg commented 4 years ago

Hi @all,

Have you tried to generate a TEMAC example design only? and check if this works? E.g. Chapter 16

stefan-niedermayr commented 4 years ago

Hi Salvatorg,

yes I'll get the same error when making a new project in coregen and trying to generate the TEMAC. Will have to investigate further.

Best regards.

20200423_coregen-fail

blacksandland commented 4 years ago

Ok - so I reconfigured my licensing on the previous kernel and still no go... I tried several workarounds in the Core Gen tool (similar to stefan-niedermayr's post) and still no go... I went back to Fedora 21 and kernel 3.17.4 -- magically I got all the dependencies installed (it wasn't working my first go around which is why I lept to a later kernel - moons are now aligned).

I got the 'make cml_cores' to run WITHOUT the trimac.xcf error this time around! So I am going to say it is a kernel issue - not knowing any better or if there is a true work around for later kernels...

However.... I am not seeing the holy grail line: //Xilinx PCIe core installed in the output...

I do however get "nf1_cml_interface installed" - is that what we are looking for?? Perhaps the kernel version is STILL too new for all this??

We can move the rest of this to a different thread if necessary (if there is indeed another issue with NOT getting the "Xilinx PCIE core installed") message - but here is my output for completeness as it pertains to this issue so others can see the differences in outputs.

With the output I received (attached) CML_cores-Build-Output.txt --> maybe Salvator can you clarify if this was successful or not??? I don't see any errors per se - but I don't see the line the getting started wiki says to look for either...

salvatorg commented 4 years ago

Hi, @blacksandland thats great that u found a workaround. The log seems to have built the trimac. Have tried to run the simulation tests? or the hardware tests?

@ All, it would be good to know which versions you used (OS, ISE, Vivado) and you have failed to generate the trimac. Can anyone replicate the workaround of @blacksandland ?

blacksandland commented 4 years ago

@Salvatorg - it appears to have failed, there were several errors in the output and I didn't get the step 4 holy grail output lines we are looking for either... Attached is the output log for reference. Not sure I should continue to the hardware tests? Or - Back to the drawing board.

Step4-ProjectBuildLog.txt

@All - Fedora 21 Kernel 3.17.4, Xilinix ISE 14.6, Xilinx Vivado 2015.2

Cheers

stefan-niedermayr commented 4 years ago

Ok, so today was one hell of a rollercoaster ride - unfortunately only partially successful. I've setup a virtualbox with Ubuntu 16.04 and installed ISE 14.6 & Vivado 2015.2. I've mapped the MAC-address to match with the registered one. The ethernet interface also required the renaming "trick". This alone brought me one step further, as the build of the TEMAC was successful. Unfortunately I run into other issues afterwards.

  1. ERROR:EDK - standalone () - couldn't execute "mb-ar":no such file or directory Solution to problem #1
  2. Missing packages Solution to problem #2

This allowed me to fully build cml_cores and make a project.

But as it turns out, the choice of Ubuntu 16.04 LTS might not have been a good one. The problem I'm currently facing is that I can't figure out how to pass the USB connection of the NetFPGA J12 USB-connection through to the virtual machine. Other USB devices, such as USB sticks and the USB FTDI 232 are recognized without a problem in the VM - no chance with the JTAG though. Even after hours of research regarding this issues, I just can't pass this USB connection through. I'm not entirely sure if its a virtualbox thing, or maybe just a driver issue. It seems that the cable drivers, allthough manually installed, are not brought up / working - I can't seem to find any windrvr6 at all. Since it is not a supported OS, i might have to bite the bullet and bring up another VM with Fedora 20, as suggested in the getting-started guide.

Nevertheless, a few steps forwards is always a good thing!

Ubuntu 16.04 LTS, 4.15.0-45-generic, Vivado 2015.2, ISE 14.6

blacksandland commented 4 years ago

@ stefan-niedermayr Can you post your output from step 3 (before your step 4 output) - if at all possible? I want to compare and see the difference to see where mine is failing... I have reconfigured this over and over with no luck on every iteration... I added every license I possibly could from Xilinx - still no joy... Thanks in advance!

stefan-niedermayr commented 4 years ago

@blacksandland Sure. Before the logs were created, I've make clean the project and the whole repo. Included the logs for make cml_cores and make of the loopback project. Hope this helps you out - so far I did not see any major errors in my build. But don't count on it, as I'm still trying to get a hang of NetFPGA projects. If you need further information, let us know.

I gave Fedora 20 a shot and created a VM. Unfortunately, USB JTAG still does not work through VirtualBox. Tomorrow I'll receive a larger SSD and will try running the VM on a Linux host and maybe give some other distros a shot. But thats another topic, not regarding this issue and not high priority, since uploading the bitstream from the hosts Vivado works just fine.

Anyway, thanks @salvatorg for helping out getting things running. If you don't mind, I'll just let this issue open until @blacksandland figures out the problem. It seems somewhat related.

Edit:

Forgot to include the files. make_cmlcores.log make_loopback.log

blacksandland commented 4 years ago

@stefan-niedermayr Thank you for the logs - they proved helpful!! I was able to generate the bit files!!! Yay! So all is good there. I ran into issues with the USB bitfile download but after a ton of trial and error - I finally got it to work! Turns out the cable that comes with the digilent 1G-CML board works better on port 12 than the usb cable that came with the jtag kit... ended up plugging both in at the same time and voila - it downloaded!

@salvatorg - I think it is likely safe to say the trimac.xcf is a kernel issue based on our results - later kernels (as advised in the wiki) just don't seem to want to play nice. I think the Wiki could be cleaned up or updated or organized a little better to streamline the process in this newer era of 1G-CML trials and tribulations. I am happy to contribute. Also the Virtual Machine approach would make a REALLY nice entry (like the laptop setup)...

Thanks for everyone's help on the trimac.xcf issue - I learned a ton along the way! Cheers - and stay healthy!