NetFPGA 1G CML Getting Started Guide - Error at Step 3

[eertraw90]

Hello,

i just tried the 'NetFPGA 1G CML Getting Started Guide' tutorial and run into an error at Step 3 (make cml_cores).

//nf1_cml_interface installed
///////////////////////////////////////////
make[1]: Leaving directory '/opt/NetFPGA/NetFPGA-1G-CML-live/lib/hw/contrib/pcores/nf1_cml_interface_v1_00_a'
make[1]: Entering directory '/opt/NetFPGA/NetFPGA-1G-CML-live/lib/hw/std/pcores/dma_v1_20_a'

****** Vivado v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source data/pcie_generate.tcl
# set project_name vivado_work
# set hdl_dir hdl/verilog/xilinx
# set ip_name pcie_7x
# exec rm -f [glob -nocomplain *.backup.jou]
# exec rm -f [glob -nocomplain *.backup.log]
# create_project -force $ip_name $project_name
# set_property part xc7k325tffg676-1 [current_project]
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
ERROR: [Coretcl 2-1133] Requested IP 'xilinx.com:ip:pcie_7x:3.1' cannot be created. 
        The latest available version in the catalog is 'xilinx.com:ip:pcie_7x:3.3'. 
        If you do not wish to select a specific version please omit the version field 
        from the command arguments, or use a wildcard in the VLNV.

Can someone help me out?

Thank you!

[yoannd]

Hello, It seems like you are using a Vivado version which is more recent that the one supported by 1G-CML. You need to update the version numbers of some IP cores (namely, pcie_7x and MIG) used by the project. The following did the trick for me:

diff --git a/lib/hw/std/pcores/dma_v1_20_a/data/pcie_generate.tcl b/lib/hw/std/pcores/dma_v1_20_a/data/pcie_generate.tcl
index 849f3ad..20d31dc 100644
--- a/lib/hw/std/pcores/dma_v1_20_a/data/pcie_generate.tcl
+++ b/lib/hw/std/pcores/dma_v1_20_a/data/pcie_generate.tcl
@@ -12,7 +12,7 @@ create_project -force $ip_name $project_name
 set_property part xc7k325tffg676-1 [current_project]

 # add PCIe IP
-set pcie_7x_xci [create_ip -name pcie_7x -vendor xilinx.com -library ip -version 3.1 -module_name pcie_7x]
+set pcie_7x_xci [create_ip -name pcie_7x -vendor xilinx.com -library ip -version 3.3 -module_name pcie_7x]

 # set desired PCIe properties
 # allow remaining properties to default
diff --git a/lib/hw/std/pcores/nf10_sram_fifo_v1_00_a/xco/mig.xco b/lib/hw/std/pcores/nf10_sram_fifo_v1_00_a/xco/mig.xco
index b2f29ee..968727f 100644
--- a/lib/hw/std/pcores/nf10_sram_fifo_v1_00_a/xco/mig.xco
+++ b/lib/hw/std/pcores/nf10_sram_fifo_v1_00_a/xco/mig.xco
@@ -38,7 +38,7 @@ SET verilogsim = true
 SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT MIG family Xilinx,_Inc. 3.6.1
+SELECT MIG family Xilinx,_Inc. 3.61
 # END Select
 # BEGIN Parameters
 CSET component_name=controller

Also, you might want to have a look at this commit, as going to version 3.3 of pcie_7x will require some code changes.

Hope that helps!

Cheers, Yoann

[aky3100]

One problem about this issue. After modifying the files pcie_generate.tcl and mig.xco, "make cml_core" seems do nothing as follows: ///////////////////////////////////////////////// //nf1_cml_interface installed //////////////////////////////////////////////// make[1]: Leaving directory /a/netfpga-1g-cml-live/lib/hw/contrib/pcores /nf1_cml_interface_v1_00_a' make[1]: Entering directory/a/netfpga-1g-cml-live/lib/hw/std/pcores/dma_v1_20_a' make[1]: Nothing to be done for all'. make[1]: Leaving directory/a/netfpga-1g-cml-live/lib/hw/std/pcores/dma_v1_20_a' make[1]: Entering directory /root/netfpga-1g-cml-live/lib/hw/std/pcores/nf10_axis_gen_check_v1_00_a' make[1]: Nothing to be done forinstall'. .... Is the PCIe core installed with this?

[salvatorg]

tried to make clean first?