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NetFPGA 1G CML Live development repository
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OpenFlow_Switch on NetFPGA 1G CML #3

Open Apiwatkrit opened 8 years ago

Apiwatkrit commented 8 years ago

Hi, I'm Apiwat. I'm student from King Mongkut's University of Technology North Bangkok

I have NetFPGA 1G-CML (Kintex-7 xc7k325T) board. I need to built openflow_switch on this board.

I downloaded source code from https://github.com/NetFPGA/ NetFPGA-1G-CML-live I modified project from NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > system.xmp by using XPS (Xilinx Platform Studio 14.6 (EDK_P.68d)) I created New BSB Project. (try to create reference_nic by myself) I can generate bit file successfully. I will add pcores(openflow_datapath_v1_00_a) into my project. I got pcores(openflow_datapath_v1_00_a) from NetFPGA-10G- Live-Master > contrib-projects > openflow_switch > hw > pcores copy to NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > pcores I know OpenFlow design has reordered the position of "input_arbiter" and removed "output_port_lookup" from NetFPGA-10G Reference NIC, instead it added "openflow_datapath" followed by "input_arbiter”. I removed “nf10_nic_output_port_lookup_v1_10_a” from NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > pcores, instead it added "openflow_datapath_v1_00_a" I try to generated bitstream. but i ended up with the following errors : ERROR:EDK:658 - BlackBox Netlist file openflow_datapath_v1_00_a/netlist/cam.ngc not foundERROR:EDK:1566 - IPNAME:openflow_datapath INSTANCE:openflow_datapath_0 - /home/apiwat/Desktop/ Project_Test_Nic/system.mhs line 505 - BBD netlist file(s) not found! ERROR:EDK:440 - platgen failed with errors! make: *\ [implementation/system_proc_sys_reset_0_wrapper.ngc] Error 2

I got into Makefile from pcores > openflow_datapath_v1_00_a > Makefile to finding cam.ngc but not found. In netlist folder of pcores > openflow_datapath_v1_00_a has file : dp_bram_32x64.ngc, dp_bram_32x384.ngc, dp_bram_1024x64.ngc, dp_bram_1024x256.ngc and dp_bram_1024x384.ngc but didn’t have cam.ngc file Please help me to fix these issues.

Thanks, Apiwat Tipakorn

I attached my project as link : https://drive.google.com/file/d/0Bwoae3LaZlwZREVpZG14d3NLbjg/view?usp=sharing My project : Project_Test_Nic OpenFlow On NetFPGA 10G : openflow_switch Openflow pcores : openflow_datapath_v1_00_a

https://drive.google.com/file/d/0Bwoae3LaZlwZVWVhWjAyS3NqUlE/view? usp=sharing NetFPGA 1G CML : NetFPGA-1G-CML-live-master NetFPGA 10G : NetFPGA-10G-live-master

davidva-cml commented 8 years ago

On 06/21/2016 11:02 AM, Apiwatkrit wrote:

Hi, I'm Apiwat. I'm student from King Mongkut's University of Technology North Bangkok

Hi Apiwat,

Please see my comments inline.

I have NetFPGA 1G-CML (Kintex-7 xc7k325T) board. I need to built openflow_switch on this board.

I downloaded source code from https://github.com/NetFPGA/ NetFPGA-1G-CML-live I modified project from NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > system.xmp by using XPS (Xilinx Platform Studio 14.6 (EDK_P.68d)) I created New BSB Project. (try to create reference_nic by myself) I can generate bit file successfully. I will add pcores(openflow_datapath_v1_00_a) into my project. I got pcores(openflow_datapath_v1_00_a) from NetFPGA-10G- Live-Master > contrib-projects > openflow_switch > hw > pcores copy to NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > pcores I know OpenFlow design has reordered the position of "input_arbiter" and removed "output_port_lookup" from NetFPGA-10G Reference NIC, instead it added "openflow_datapath" followed by "input_arbiter”. I removed “nf10_nic_output_port_lookup_v1_10_a” from NetFPGA-1G-CML-live-master > projects > reference_nic_nf1_cml > hw > pcores, instead it added "openflow_datapath_v1_00_a" I try to generated bitstream. but i ended up with the following errors : ERROR:EDK:658 - BlackBox Netlist file openflow_datapath_v1_00_a/netlist/cam.ngc not foundERROR:EDK:1566 - IPNAME:openflow_datapath INSTANCE:openflow_datapath_0 - /home/apiwat/Desktop/ Project_Test_Nic/system.mhs line 505 - BBD netlist file(s) not found! ERROR:EDK:440 - platgen failed with errors! make: *\ [implementation/system_proc_sys_reset_0_wrapper.ngc] Error 2

I got into Makefile from pcores > openflow_datapath_v1_00_a > Makefile to finding cam.ngc but not found. In netlist folder of pcores > openflow_datapath_v1_00_a has file : dp_bram_32x64.ngc, dp_bram_32x384.ngc, dp_bram_1024x64.ngc, dp_bram_1024x256.ngc and dp_bram_1024x384.ngc but didn’t have cam.ngc file Please help me to fix these issues.

Instructions for generating and using the CAM netlists (cam.ngc) using Xilinx's CAM generator can be found in projects/reference_switch_nf1_cml/README.

Note that some of the parameters for the CAM generator, such as width, depth, and modes, may be different between the reference_switch_nf1_cml and the OpenFlow switch. The directions for the 10G OpenFlow switch may provide the necessary values. However, you will at least need to follow the instructions in the README above to patch the CAM generator for use with the Kintex 7 FPGA on the NetFPGA-1G-CML.

A number of users have been interested in the OpenFlow switch on the NetFPGA-1G-CML. If you are able to contribute it when you have completed the porting process, it would be a valuable addition to the code base.

Finally, we offer a support mailing list for the NetFPGA-1G-CML, which can be joined by completing the form at the following link:

https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-cml-beta

Please consider using this for further queries, as more users watch that list than the Github issues page.

Thanks, David Van Arnem

Thanks, Apiwat Tipakorn

I attached my project as link : https://drive.google.com/file/d/0Bwoae3LaZlwZREVpZG14d3NLbjg/view?usp=sharing My project : Project_Test_Nic OpenFlow On NetFPGA 10G : openflow_switch Openflow pcores : openflow_datapath_v1_00_a

https://drive.google.com/file/d/0Bwoae3LaZlwZVWVhWjAyS3NqUlE/view? usp=sharing NetFPGA 1G CML : NetFPGA-1G-CML-live-master NetFPGA 10G : NetFPGA-10G-live-master

You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/NetFPGA/NetFPGA-1G-CML-live/issues/3

Thanks, David Van Arnem Development Engineer Computer Measurement Laboratory