Open onlyfly34 opened 6 years ago
This workflow only supports the NetFPGA SUME platform at the moment. There is no reason why you cannot use a P4-described SDNet-generated block in the old 1G board, but it would require some integration effort. The P4-NetFPGA workflow as it currently stands assumes use of the Vivado toolchain and the NetFPGA SUME simulation infrastructure.
As the title. Is there any solution?