Open nniranjhana opened 5 years ago
Hi, You can try to reduce the time using incremental design. Check this AR https://www.xilinx.com/support/answers/57853.html out. You need the dcp from the original project. I'm not sure how much time you can reduce.
Hey @mariodruiz Thanks for this, I'll check this out, wasn't aware of it earlier.
Hi, we were following the switch tutorial for compiling P4 to NetFPGA. And we noticed that it takes around a couple of hours to generate the bit file. Is there a way to reduce this time? Since we'd have to recompile for any small change in the P4 program.