sdnet simulation fail in P4 compilation

We have created our own P4 project, and wrote the corresponding gen_testdata.py and also modified the header file appropriately. But we keep getting the error:

Error: Single Control Port option is invalid, if there are no access ports within the design.

We are unable to find any info regarding this error and hence can't proceed. What could be the issue? Find below relevant code from files (P4 file attached as .txt):

_gentestdata.py:

#####################
# generate testdata #
#####################
MAC1 = "08:11:11:11:11:08"
MAC2 = "08:22:22:22:22:08"

def create_data(CTRL_INFO, FRWD_TAG_PRT): 
    pktCnt = 0
    pkt = Ether(dst=MAC2, src=MAC1) / Calc(ctrl_info=CTRL_INFO, frwd_tag_prt=FRWD_TAG_PRT)
    pkt = pad_pkt(pkt, 64)
    applyPkt(pkt, 'nf1', pktCnt)
    pktCnt += 1
    expPkt(pkt, 'nf1')

create_data(0, 4)

header file:

class Calc(Packet):
    name = "Calc"
    fields_desc = [
        IntField("ctrl_info", 0),
        IntField("frwd_tag_prt", 0),
    ]
    def mysummary(self):
        return self.sprintf("ctrl_info=%ctrl_info% frwd_tag_prt=%frwd_tag_prt%")

bind_layers(Ether, Calc, type=CALC_TYPE)
bind_layers(Calc, Raw)

Error on console:

/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu$ make
make -C src/ clean
make[1]: Entering directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/src'
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
make[1]: Leaving directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/src'
make -C testdata/ clean
make[1]: Entering directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/testdata'
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
make[1]: Leaving directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/testdata'
rm -rf nf_sume_sdnet_ip/
rm -f 
rm -f sw/config_tables.c
make -C src/
make[1]: Entering directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/src'
p4c-sdnet -o smartho_cu.sdnet --sdnet_info .sdnet_switch_info.dat smartho_cu.p4
/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
make[1]: Leaving directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/src'
make -C testdata/
make[1]: Entering directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/testdata'
./gen_testdata.py
WARNING: No route found for IPv6 destination :: (no default route?)
nf0_applied times:  []
nf1_applied times:  [0]
nf2_applied times:  []
nf3_applied times:  []
/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
WARNING: No route found for IPv6 destination :: (no default route?)
/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
WARNING: No route found for IPv6 destination :: (no default route?)
make[1]: Leaving directory `/home/fpga/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/smartho_cu/testdata'
sdnet ./src/smartho_cu.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
Xilinx SDNet Compiler version 2018.1.1, build 2258648

*** Error: Single Control Port option is invalid, if there are no access ports within the design.

make: *** [compile_no_cpp_test] Error 1

smartho_cu.p4.txt

NetFPGA / P4-NetFPGA-public

sdnet simulation fail in P4 compilation #20