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INT tutorial assignment hwtest not working as expected #28

Closed harshgondaliya closed 5 years ago

harshgondaliya commented 5 years ago

I have exactly writtenint.p4as the int_solution.p4 (verified using diff tool). I am able to pass all the simulation tests. Bit file is also generated successfully.

Now, when I try to run hardware test, I am not able to see the desired functionality. Packets are getting sent using the int_tester.py script but no packets are received using rcv_int.py file. I suspect the packets are getting dropped at the NetFPGA SUME board.

I have used slightly different topology than what was recommended. My SUME board is connected on one PC while the two-port 10G card is on another PC. But, I have made sure nf0 is connected to eth1 and nf1 is connected to eth2.

Used Vivado 2018.2 & SDNet Compiler 2018.1.1

harshgondaliya commented 5 years ago

I think there is some typecasting issue in int_solution.p4and int.p4 Original Code:

    action set_output_port(port_t port) {
        sume_metadata.dst_port = port;
    }

My Changes:

   typedef bit<8> my_port_t; 
   action set_output_port(my_port_t port) {
        sume_metadata.dst_port = port;
    }

After making this change hardware test worked as expected. I want to know bit-width of port_t that is used in original P4 code. Can any repository member please look into this?

harshgondaliya commented 5 years ago

There is no typecasting fault. port_t is bit<8>. Since this issue is more relavant for P4-NetFPGA-live repository, I am closing this issue here and asking it on the other repository.