Closed hesingh closed 5 years ago
Hi Hemant,
Extending the P4 language and associated compiler to allow developers to express custom architectures is indeed an area of active research. I'll be demoing a prototype of the Programmable Target Architectures (PTA) tool at the upcoming P4EU Workshop. The PTA tool is still a work in progress and is developed on top of the latest version of SDNet, which hasn't been released yet. Once everything becomes stable, I plan to incorporate the PTA tool into the P4->NetFPGA Workflow.
For the time being, there is a branch in the P4-NetFPGA-live repo with a project called double_ingress, which contains two P4-SDNet generated modules connected back-to-back prior to the output queues module. So the new NetFPGA datapath is:
Input Arbiter --> P4 Ingress1 --> P4 Ingress2 --> Output Queues
Each Ingress pipeline is a P4-SDNet module which is generated by writing a separate P4 program for the SimpleSumeSwitch Architecture. You can use the project as a rough guide for the necessary steps to take to add additional P4 modules, but this certainly isn't the cleanest solution. That being said, the SDNet and SUME simulations are all passing so the functionality appears to be correct.
Best, Steve
Steve, The 'double_ingress' link you added in your note is not found.
thanks for the details.
Best,
Hemant
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Thanks! I just filled out the registration form.
Dear @sibanez12, anything new for the PTA Tools? could you share the current status of PTA Tool development?
Thanks.
The P4 language extensions to describe target architectures is being discussed within the P4 community. After the extensions have been settled upon and the new SDNet compiler is released, then we can make further progress on developing the PTA tool.
Thanks @sibanez12 ,
I see that the FPGA supports a Parser, Match-Action block, and Deparser. Is Xilinx SDNET and tools able to handle arbitrary P4 architectures such as in Figure 4 of the P4-16 specification:
https://p4.org/p4-spec/docs/P4-16-v1.0.0-spec.html
For example, I would add a few more P4 blocks between the Parser and Deparser.