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Access to the scheduler/PRE code? #5

Open gopchandani opened 5 years ago

gopchandani commented 5 years ago

Hi,

We are wanting to adopt this workflow for a project.

Wondering if we get access to the code that drives packet scheduling as part of this workflow? We are wanting to tinker with the PRE. One imagines that the workflow comes with a certain flavor, but is it modifiable? Is the code for the same available in the public domain?

- Rakesh

sibanez12 commented 5 years ago

Hi Rakesh,

The packet scheduling code is indeed openly available. It is implemented in Verilog and performs simple FIFO scheduling for each output port.

Best, Steve

gopchandani commented 5 years ago

Hey Steve,

Thanks!

  1. Where can I find it?
  2. Is there a mechanism/API/compiler whereby the schedule can be expressed in C instead of Verilog?

- Rakesh

sibanez12 commented 5 years ago

Check out the sss_output_queues module in the P4-NetFPGA-live repo. Note that you'll need to register for access to the repo (see the Getting Started Guide).

You can try to implement the scheduler in Vivado HLS and then replace the sss_output_queues module with the HLS generated IP module. That's not something that I've tried before, but I think it should be possible.

Out of curiosity, what kind of scheduling algorithms do you want to experiment with?

gopchandani commented 5 years ago

Thanks! Just requested registration.

So, the goal of our project is to provide guarantees for real-time traffic. The starting point would be strict priority scheduling

Beyond that, we want to see if it is possible to read the contents of packet headers (e.g. INT headers) in the scheduler and how knarly that could get. So, need some exploration there. Do you have any thoughts about that?

sibanez12 commented 5 years ago

If you're comfortable working with FPGAs and Vivado then I think this is a feasible approach.

One thing that might be interesting is to explore whether or not you can express your scheduling algorithms within the PIFO framework. I recently prototyped a PIFO on the NetFPGA (although it's not publicly available yet).

Also I wanted to point out that unless you are particularly tied to prototyping on NetFPGA you might want to consider using ns3-bmv2, which is something that I've been working on recently to integrate the open source P4 bmv2 into NS3. I'm using it at the moment to prototype qdisc implementations in P4 (see the red prototype as an example). Currently P4 programs can only be used to implement drop policies (i.e. active queue management), but I hope to enable P4 programmable scheduling and shaping as well within this same framework.