Set up sample project for card fpga with modified SPI core and do a comms test with backplane

NeuronRobotics / mribot-issues

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Set up sample project for card fpga with modified SPI core and do a comms test with backplane #4

Closed acamilo closed 9 years ago

acamilo commented 9 years ago

Made a PLL and bosted clock to 200mhz. ran this into SPI_Slave core. Set TX data to 0xBAADBEEF Still getting FFs

acamilo commented 9 years ago

UART still works.

acamilo commented 9 years ago

checked w scope. SS (sync) is always high. SCK and SDI contain data. why is SS not going low. Wired output of spi slave RX'd word to UART debug printer to see what the other end RX'd. it shows all zeroes.

checking SPI example code

acamilo commented 9 years ago

XSpi_SetSlaveSelect is index 1 with 0 bieng nothing selected. working. Card sends back 16words 0xBAADBEEF (set in HDL) and backplane sends 16 words 0xC0FFE00*[0-F]. set in test code. i can see the data on the jtag console and uart respectively.