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Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
MIT License
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VHDL: cannot visit NULL statement #147

Closed andrasm62 closed 3 years ago

andrasm62 commented 3 years ago

Hello!

I tried to parse a VHDL file that contains a CASE statement with a NULL statement. An example from VHDL Reference Guide:

case ENCRYPTION is
  when "00" => 
    CPU_DATA_TMP := (B & A) - OPERAND;
  when "01" => 
    CPU_DATA_TMP := (B & A) + OPERAND;
  when "10" => 
    CPU_DATA_TMP := (A & B) - OPERAND; 
  when "11" => 
    CPU_DATA_TMP := (A & B) + OPERAND;
  when others =>
    null;
end case;

I think adding to hdlConvertorAst.to.common.py.visit_iHdlExpr() the elif is None: w('NULL') will solve the issue.

Nic30 commented 3 years ago

I think adding to hdlConvertorAst.to.common.py.visit_iHdlExpr() the elif is None: w('NULL') will solve the issue.

Yes that was one of the possibilities however there is a HdlStmNop which should be used instead as it is HDL language independent.

It should work now.

andrasm62 commented 3 years ago

It seems to work! Thank you!