VHDL: open is not handled correctly when trying to write AST to VHDL

[Partidani]

Hi,

trying to parse and rewrite a VHDL from the AST. As title says, open keyword is not handled correctly in port associations. Parsing is successful, but the output stream stops at the point where the open keyword was in the original source.

Use case:

foo_ins: entity work.foo
    generic map (
        a => 4
    )
    port map (
        clk => clk,
        b => open
    );

Output:

foo_ins: work.foo GENERIC MAP(
        a => 4
    )
    PORT MAP(
        clk => clk,
        b => 

[Nic30]

Fixed in #156