Open Thomasb81 opened 2 years ago
test_hier_delay_value.sv.tar.gz SystemVerilog grammar of hdlConvertor failed to parse the attached testcase.
Apparently following syntax is right... LRM seems incomplete. the syntax is accepted and simulation is run by several commercial simulator.
But systemVerilog grammar of hdlConvertor does not allow this (aka hierarchical identifier for a delay value (delay_value rule )
delay_value
module test_module0(); identifier1 test_module1(); initial begin $display("%t start",$time); #identifier1.identifier2.identifier3; $display("%t end",$time); end endmodule
test_hier_delay_value.sv.tar.gz SystemVerilog grammar of hdlConvertor failed to parse the attached testcase.
Apparently following syntax is right... LRM seems incomplete. the syntax is accepted and simulation is run by several commercial simulator.
But systemVerilog grammar of hdlConvertor does not allow this (aka hierarchical identifier for a delay value (
delay_value
rule )