Using updated SV/Verilog, VHDL Grammars

[AmeyaVS]

While working on #176 , and the issue I faced with dummy module missing instance name not generating a parse error seems to be related to the existing grammar being used.

Would it make sense to update the grammar for SV/Verilog, and VHDL from the official ANTLR4 repo: https://github.com/antlr/grammars-v4

• https://github.com/antlr/grammars-v4/tree/master/verilog
• https://github.com/antlr/grammars-v4/tree/master/vhdl

I would like to know if it makes sense.

[Nic30]

It may be beneficial for ANTLR4 repo, there were people asking for this hdlConvertor grammar because it is much faster. But I never had the time to actually commit it to that repo.

But there is a problem. Grammars in hdlConvertor do have inlined c++ peredicates. Although they are mostly not necessary and it is possible to write grammar without them they are present mostly from performance reasons. https://github.com/Nic30/hdlConvertor/blob/master/grammars/sv2017Lexer.g4#L37 They are also often tied to some small code which is stored in the repo and my guess is that people from ANTLR4 do accept only pure ANTLR4 grammars. But I did not ask so I do not know.

So, yes, it makes sense but it requires consultation with someone from https://github.com/antlr/grammars-v4/ what to do about inlined C++ predicates.

[AmeyaVS]

I think it would be best if we can get some feedback from the ANTLR4 Grammar Community. Let me see if I can spend some updating some part of the grammar, but there is no guarantee it would be ready any time soon, as I am quite new to ANTLR.