tests+verilog preproc: Fix ANTLR <=4.9, CMake and Icarus tests

Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

MIT License

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tests+verilog preproc: Fix ANTLR <=4.9, CMake and Icarus tests #186

Closed kleinesfilmroellchen closed 5 months ago

kleinesfilmroellchen commented 6 months ago

ANTLR 4.9 antlrcpp::Any was used incorrectly, preventing it from compiling on e.g. 4.9.3
Depending on the compiler and CMake version used, C++ 17 wouldn't be automatically selected for the project.
Icarus moved the test file "sv_macro3" to two separate versions (a and b), but this is not yet correctly reflected in their file lists. With this change, all ~7000 tests collect correctly again under pytest and concurrencytest.

Nic30 commented 6 months ago

@kleinesfilmroellchen Helo and thank you for your contribution. Currently I replaced cmake with meson build and I also fixed issue which is causing test on your pull request to fail. So there is no problem with your commit. However I am stuck at figuring out how to configure coverage reporting in meson build correctly. https://app.circleci.com/pipelines/github/Nic30/hdlConvertor/157/workflows/f7e5cb0a-257e-4925-af32-df570d79eef6/jobs/223 https://github.com/Nic30/hdlConvertor/blob/mesonbuild/.circleci/config.yml#L51

So if you can help me with that we can merge immediately.

kleinesfilmroellchen commented 5 months ago

@Nic30 sorry for the delay, but I am not at all familiar with Meson. Since I won't be able to use upstream for other reasons anyways, it doesn't matter to me whether you merge this or not, I was just interested in contributing some of my fixes upstream.

Nic30 commented 5 months ago

@kleinesfilmroellchen

I won't be able to use upstream

May I ask for more details?

kleinesfilmroellchen commented 5 months ago

@kleinesfilmroellchen

I won't be able to use upstream

May I ask for more details?

The CMake configuration needs to be adjusted to use the correct ANTLR file; it can't find the one I'm trying to provide it despite my best efforts. You really shouldn't worry about this, it's a weird setup for a one-time project that doesn't even use most of hdlConvertor (namely none of the "universal HDL" IR stuff since it's incompatible with important SystemVerilog features like user-defined types)

kleinesfilmroellchen commented 5 months ago

Thanks!