Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
MIT License
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character literals / enumeration literals #61

Closed imec-myhdl closed 5 years ago

imec-myhdl commented 5 years ago

character literals ('0', '1', 'Z' etc) are converted to an integer in line 176 of src/vhdlConvertor/literalParser.cpp by subtracting the value '0' This produces 'weird' results for anything else than '0' and '1'. for example std_logic is predefined enumeration('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') Also the bit width is set to 8 (in line 168 of the same file).

Solving is probably easiest by doing a 2-step (visitor) approach: during the first visit do type annotation (like in myhdl) where signal/variable types/widths/initvalues/signed are resolved (in the myhdl case relevant info is stored in attributes of the nodes, but that is dynamic, so might not be the best approach in cpp, During the second visit the type is known, and conversion is relatively simple.

Nic30 commented 5 years ago

Problems:

I will change mentioned code to represent char literals with bitstring instead (so the value is always correct). And I will add a flag which signalizes that this was char literal (so it is easy to convert it back without code analysis).