Nic30 hdlConvertorAst issues - Githubissues

Nic30 / hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

MIT License

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How HDLConvertorAst support SystemVerilog

#8 fzwwj95 closed 1 year ago
1
Verilog or System Verilog：How could I get the pure Verilog code without System Verilog syntax?

#7 Hovennnnn opened 1 year ago
1
SystemVerilog: multiple packed dimensions not processed correctly

#6 theo-scott opened 2 years ago
2
HdlStmIf: cond, if_true property useless

#5 Nic30 opened 3 years ago
0
Adding support for VHDL physical types

#4 mewais closed 3 years ago
1
localparam with operator **

#3 dramoz closed 3 years ago
2
PackageParser.visitConstant_declaration Conversion to Python object not implemented

#2 mewais closed 3 years ago
8
Error when call visit_HdlContext NotImplementedError: Unexpected object of type

#1 jinfuchen closed 3 years ago
5