Value of param at top level is invalid

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

194 stars 26 forks source link

Closed Nic30 closed 8 years ago

Nic30 commented 8 years ago

ENTITY AxiLiteSlaveContainer IS
    GENERIC (
        ADDR_WIDTH : INTEGER := <Param, val=8>;
        DATA_WIDTH : INTEGER := <Param, val=8>
...