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Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
194 stars 26 forks source link

Help with design low-level HDL language #13

Closed XVilka closed 5 years ago

XVilka commented 5 years ago

FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations will opt only for generating this low-level HDL and routing/synthesizers accept it. LLVM or WebAssembly - you can see how many languages and targets are supported now by both. With more open source tools for FPGA this is more feasible now than ever.

See SymbiFlow/ideas#19

Nic30 commented 5 years ago

Hello @XVilka , I responded in issue SymbiFlow/ideas#19 .

It is quire clear we need it, I am ready to help. As you know LLVM contains tons of utilities used in compiler development. I think that this is the work the open hardware community should do right now. Because FIRRTL and other FPGA-assembly-like languages exists and the problems are the operations which are used in optimizations.

I am not satisfied in features of Scala programming language or it's "packaging systems". It would be nice to have C++ implementation with only binding to Scala (java native api), Python and others.

The most important aspect of your plan is persecute the peoples that your unfinished project will become mainstream. Because otherwise everyone write thousands of lines of the code like you did and will stick with it and will never use your project.

It may seems like hey chisel3 is there more 10 years and it's popularity is growing, maybe it just takes long. But true is that this project is alive because very large number of companies, universities and individuals are using it. Which is not the case of your potential project. I mean you have to act fast. This project still has some features which no one has, but project like magma just decidet to do same thing because they were not aware of this project. Maybe the same as me when there was a SpinalHDL.

Also remember that the generation of the hardware is the smallest problem. Verification/simulation are the things which takes much more time.

Nic30 commented 5 years ago

Closing this issue as we are solving it in referenced issue. Also It seems that everyone knows what to do (Use FIRRTL). It is required to write FIRRTL library in C++ with Python3 wrapper and maybe Rust wrapper/java wrapper would be useful as well. I expect that I will do it during the Christmas. (But problems will always appear.)

XVilka commented 5 years ago

Agree. Thanks for the idea support!