params are not set on component instances

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

MIT License

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params are not set on component instances #2

Closed Nic30 closed 8 years ago

Nic30 commented 8 years ago

Axi_basic_slave_140321357064568 : COMPONENT Axi_basic_slave
    GENERIC MAP (
        C_S_AXI_ADDR_WIDTH => 4,
        C_S_AXI_DATA_WIDTH => 32
...

class AxiLiteSlaveContainer(Unit):
    ADDR_WIDTH = Param(8)
    DATA_WIDTH = Param(8)
    ...
    slv.C_S_AXI_ADDR_WIDTH.inherit(ADDR_WIDTH)
    slv.C_S_AXI_DATA_WIDTH.inherit(DATA_WIDTH)

Nic30 commented 8 years ago

fixed