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Nic30
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hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
MIT License
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Proper tutorial - simulations/verifications
#27
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Nic30
opened
4 years ago
Nic30
commented
4 years ago
UVM basics
Automatic simulation setup in unittest.TestCase subclass.
Automatic prepare without automatic execution, agent,clk, rst,... to an interface associations
UVM stages equivalents
Custom interface agent, hierarchical agents
Randomization
parallelization, cloud
Nic30
commented
3 years ago
https://github.com/Nic30/jupyter_widget_hwt/tree/master/examples